US 2006/0139996 A1 · Dynamic data restore in thyristor-based memory device

Abstract

A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

Claims20

Dependent claims

A semiconductor device comprising:

a memory cell comprising a thyristor disposed electrically in series with an access device;
and
a restore circuit operable to apply periodic pulses to the memory cell to maintain its data state.

A thyristor-based semiconductor memory device comprising:

a plurality of memory cells disposed in an array of rows and columns;
a plurality of bit lines associated with the respective columns of the array;
at least one memory cell of the plurality comprising:
a thyristor;
a MOSFET comprising a gatable channel disposed serially between the thyristor and a given bit line of the plurality for the column associated with the memory cell;
and
a capacitor electrode capacitively coupled to a base region of the thyristor;
a plurality of first wordlines associated with respective rows to the array, a given first wordline of the plurality to a given row coupled to the gates of the MOSFETs across said row;
a plurality of second wordlines associated with the respective rows to the array, a given second wordline of the plurality to a given row coupled to the capacitor electrodes to the thyristors across said row;
and
a restore circuit to periodically pulse at least one of the first wordlines, the second wordlines, and the bit lines to maintain data per the bi-stable operability of the thyristor(s) of at least one of the memory cells of the array.

8 more elements

Dependencies are inferred from the claim text.

Dynamic data restore in thyristor-based memory device

Life of this patent

Dynamic data restore in thyristor-based memory device

Life of this patent

Abstract

Claims20