Non-volatile semiconductor storage device performing ROM read operation upon power-on

Abstract

A power-on reset circuit has a power-on level detecting circuit which detects a power voltage to output a power-on reset signal and a delay circuit which delays the power-on reset signal output by the power-on level detecting circuit. Two chip address specifying pads are connected to the delay circuit. Delay time in the delay time is controlled according to a chip address supplied to these two pads.

Dependencies are inferred from the claim text.