Capacitor design for controlling equivalent series resistance
AssigneeIntel Corporation
InventorsYuan-Liang Li, David Figueroa, Farzaneh Yahyaei-moayyed, Dong Zhong
Life of this patent
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Abstract
According to some embodiments, a capacitor includes a first external capacitor plane comprising a first at least one terminal of a first polarity, and a first internal capacitor plane comprising a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.
Claims22
A capacitor comprising:
- a first external capacitor plane comprising a first at least one terminal of a first polarity;
- and
- a first internal capacitor plane comprising a second at least one terminal of the first polarity, the second at least one terminal of the first polarity being electrically coupled to the first at least one terminal of the first polarity,
- wherein a total area of the second at least one terminal of the first polarity is less than a total area of the first at least one terminal of the first polarity.
A method comprising:
- fabricating a first external capacitor plane comprising a first at least one terminal of a first polarity;
- fabricating a first internal capacitor plane comprising a second at least one terminal of the first polarity, a total area of the second at least one terminal of the first polarity being less than a total area of the first at least one terminal of the first polarity;
- and
- electrically coupling the second at least one terminal of the first polarity to the first at least one terminal of the first polarity.
A system comprising:
- a microprocessor die;
- an integrated circuit package coupled to the microprocessor die;
- a decoupling capacitor coupled to the integrated circuit package, the decoupling capacitor comprising:
- a first external capacitor plane comprising a first at least one terminal of a first polarity;
- and
- a first internal capacitor plane comprising a second at least one terminal of the first polarity, the second at least one terminal of the first polarity being electrically coupled to the first at least one terminal of the first polarity, a total area of the second at least one terminal of the first polarity being less than a total area of the first at least one terminal of the first polarity;
- and
- a double data rate memory coupled to the integrated circuit package.
Dependencies are inferred from the claim text.