Limiter circuit and semiconductor integrated circuit thereof
OwnerTakefumi Nishimuta, Hiroshi Miyagi +3inventors
InventorsTakefumi Nishimuta, Hiroshi Miyagi, Tadahiro Ohmi, Shigetoshi Sugawa, Akinobu Teramoto
Life of this patent
Estimating the term…
Abstract
A rectangular parallelepiped p-channel MOS transistor 21 having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the p-channel MOS transistor 21. A source and a drain are formed on both sides of a gate electrode 26 to form a MOS transistor. A differential amplification circuit including MOS transistors 61 and 62 configures a limiter circuit. Thus, the gain of the limiter circuit can be designed large.
Claims8
A limiter circuit formed on a semiconductor integrated circuit substrate, comprising:
- a differential amplification circuit comprising an MIS field-effect transistor in which a projecting portion is formed by a silicon substrate having a first crystal surface as a primary surface and a second crystal surface as a side surface, terminated hydrogen on the silicon surface is removed in plasma atmosphere of an inert gas, then a gate insulating film is formed on at least a part of a top surface and the side surface of the projecting portion at a temperature at or lower than about 550° C. in the plasma atmosphere, a gate is formed on the gate insulating film, and a drain and a source are formed on both sides enclosing the gate insulating film of the projecting portion.
A semiconductor integrated circuit comprising on a same circuit substrate:
- a circuit comprising a p-channel MIS field-effect transistor and an n-channel MIS field-effect transistor in which a projecting portion is formed by a silicon substrate having a first crystal surface as a primary surface and a second crystal surface as a side surface, terminated hydrogen on the silicon surface is removed in plasma atmosphere of an inert gas, then a gate insulating film is formed on at least one of the top surface and the side surface of the projecting portion at a temperature at or lower than about 550° C. in the plasma atmosphere, a gate is formed on the gate insulating film, and a drain and a source are formed on both sides enclosing the gate insulating film of the projecting portion;
- and
- a limiter circuit comprising a differential amplification circuit having the p-channel MIS field-effect transistor or the n-channel MIS field-effect transistor.
Dependencies are inferred from the claim text.