Shift register and liquid crystal display device using the same
AssigneeLG. Philips LCD Co., Ltd.
InventorNam Cho
Life of this patent
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Abstract
A shift register and an LCD device to prevent the deterioration of a transistor by controlling a bias stress are disclosed. The shift register includes a plurality of stages for sequential shift signals, wherein each of the plurality of stages is connected with first and second supplying voltage input lines having opposite phases inversed by at least every frame, a start pulse input line, and at least one clock signal input line in which a phase of a first logic state is shifted in sequence, and a clock signal inputted to the clock signal input line is maintained in a second logic state different from the first logic state during a blanking time between frames.
Claims34
A shift register comprising:
- a plurality of stages for sequential shift signals, wherein each of the plurality of stages is connected with first and second supplying voltage input lines having opposite phases inversed by at least every frame;
- a start pulse input line;
- and
- at least one clock signal input line in which a phase of a first logic state is shifted in sequence, and a clock signal inputted to the clock signal input line is maintained in a second logic state different from the first logic state during a blanking time between frames.
An LCD device comprising:
- an LCD panel including liquid crystal cells in pixel regions defined by a plurality of gate lines and a plurality of data lines;
- a data driver for supplying data to the data lines;
- a gate driver including a plurality of stages, wherein each of the plurality of stages, connected with a start pulse input line and at least one clock signal input line for sequentially shifting phases of a first logic state, generates scan pulses for driving the plurality of gate lines;
- and
- a timing controller for controlling the data driver and the gate driver, and generating a clock mask signal corresponding to a blanking time, wherein the blanking time is a period between frames;
- wherein the clock signal is maintained in a second logic state different from the first logic state during the blanking time according to the clock mask signal.
A method for operating an LCD display comprising an LCD panel including liquid crystal cells in pixel regions defined by data lines and gate lines, the method comprising:
- supplying data to the data lines form a data driver;
- generating scan pulses for driving the gate lines from a gate driver, the gate driver including a plurality of stages, wherein each of the plurality of stages is connected with a start pulse input line and at least one clock signal input line for sequentially shifting phases of a first logic state;
- controlling the data driver and the gate driver with a timing controller;
- generating a clock mask signal corresponding to a blanking time;
- and
- maintaining the clock signal in a second logic state during the blanking time according to the clock mask signal, wherein the second logic state is different from the first logic state.
Dependencies are inferred from the claim text.