Driving circuit including shift register and flat panel display device using the same

A shift register of a driving circuit for a flat panel display device having a plurality of stages, comprising:

• a first thin film transistor (TFT) receiving an output voltage of a previous stage and connected to a Q node, the first TFT having a diode structure such that a gate electrode of the first TFT is connected to a drain electrode of the first TFT;
• a second TFT between the Q node and a supply voltage terminal, the second TFT switched according to an output voltage of a next stage;
• a third odd-first TFT between an odd source voltage terminal and a QB-o node, the third odd-first TFT having a diode structure such that a gate electrode of the third odd-first TFT is connected to a drain electrode of the third odd-first TFT;
• a third odd-second TFT between the odd source voltage terminal and the QB-o node, the third odd-second TFT switched according to a voltage of a first node;
• a third odd-third TFT between the first node and the supply voltage terminal, the third odd-third TFT switched according to a voltage of the Q node;
• a third odd-fourth TFT between the first node and the supply voltage terminal, the third odd-fourth TFT switched according to the output voltage of the previous stage;
• a third even-first TFT between an even source voltage terminal and a QB-e node, the third even-first TFT having a diode structure such that a gate electrode of the third even-first TFT is connected to a drain electrode of the third even-first TFT;
• a third even-second TFT between the even source voltage terminal and the QB-e node, the third even-second TFT switched according to a voltage of a second node;
• a third even-third TFT between the second node and the supply voltage terminal, the third even-third TFT switched according to a voltage of the Q node;
• a third even-fourth TFT between the second node and the supply voltage terminal, the third even-fourth TFT switched according to the output voltage of the previous stage;
• a fourth TFT between a first clock terminal and an output voltage terminal of a present stage, the fourth TFT switched according to a voltage of the Q node;
• a fifth odd TFT between the QB-o node and the supply voltage terminal, the fifth odd TFT switched according to the voltage of the Q node;
• a fifth even TFT between the QB-e node and the supply voltage terminal, the fifth even TFT switched according to the voltage of the Q node;
• a sixth odd TFT between the QB-o node and the supply voltage terminal, the sixth odd TFT switched according to the output voltage of the previous stage;
• a sixth even TFT between the QB-e node and the supply voltage terminal, the sixth even TFT switched according to the output voltage of the previous stage;
• a seventh odd TFT between the Q node and the supply voltage terminal, the seventh odd TFT switched according to a voltage of the QB-o node;
• a seventh even TFT between the Q node and the supply voltage terminal, the seventh even TFT switched according to a voltage of the QB-e node;
• an eighth odd TFT between the output voltage terminal of the present stage and the supply voltage terminal, the eighth odd TFT switched according to the voltage of the QB-o node;
• and
• an eighth even TFT between the output voltage terminal of the present stage and the supply voltage terminal, the eighth even TFT switched according to the voltage of the QB-e node.

A shift register of a driving circuit for a flat panel display device having a plurality of stages, comprising:

• a first thin film transistor (TFT) receiving an output voltage of a previous stage and connected to a Q node, the first TFT having a diode structure such that a gate electrode of the first TFT is connected to a drain electrode of the first TFT;
• a second TFT between the Q node and a supply voltage terminal, the second TFT switched according to an output voltage of a next stage;
• a third odd-first TFT between an odd source voltage terminal and a QB-o node, the third odd-first TFT having a diode structure such that a gate electrode of the third odd-first TFT is connected to a drain electrode of the third odd-first TFT;
• a third odd-second TFT between the odd source voltage terminal and the QB-o node, the third odd-second TFT switched according to a voltage of a first node;
• a third odd-third TFT between the first node and the supply voltage terminal, the third odd-third TFT switched according to a voltage of the Q node;
• a third odd-fourth TFT between the first node and the supply voltage terminal, the third odd-fourth TFT switched according to the even source voltage;
• a third even-first TFT between an even source voltage terminal and a QB-e node, the third even-first TFT having a diode structure such that a gate electrode of the third even-first TFT is connected to a drain electrode of the third even-first TFT;
• a third even-second TFT between the even source voltage terminal and the QB-e node, the third even-second TFT switched according to a voltage of a second node;
• a third even-third TFT between the second node and the supply voltage terminal, the third even-third TFT switched according to a voltage of the Q node;
• a third even-fourth TFT between the second node and the supply voltage terminal, the third even-fourth TFT switched according to the odd source voltage;
• a fourth TFT between a first clock terminal and an output voltage terminal of a present stage, the fourth TFT switched according to a voltage of the Q node;
• a fifth odd TFT between the QB-o node and the supply voltage terminal, the fifth odd TFT switched according to the voltage of the Q node;
• a fifth even TFT between the QB-e node and the supply voltage terminal, the fifth even TFT switched according to the voltage of the Q node;
• a sixth odd TFT between the QB-o node and the supply voltage terminal, the sixth odd TFT switched according to the output voltage of the previous stage;
• a sixth even TFT between the QB-e node and the supply voltage terminal, the sixth even TFT switched according to the output voltage of the previous stage;
• a seventh odd TFT between the Q node and the supply voltage terminal, the seventh odd TFT switched according to a voltage of the QB-o node;
• a seventh even TFT between the Q node and the supply voltage terminal, the seventh even TFT switched according to a voltage of the QB-e node;
• an eighth odd TFT between the output voltage terminal of the present stage and the supply voltage terminal, the eighth odd TFT switched according to the voltage of the QB-o node;
• and
• an eighth even TFT between the output voltage terminal of the present stage and the supply voltage terminal, the eighth even TFT switched according to the voltage of the QB-e node.

A plurality of shift register stages of a driving circuit for a flat panel display device, comprising:

• a first thin film transistor (TFT) charging a Q node according to a start signal;
• a second TFT discharging the Q node according to an output voltage of a next shift register stage;
• a pull-up unit increasing an output voltage of a present shift register stage according to a voltage of the Q node;
• an odd pull-down unit decreasing the output voltage of the present stage in an odd frame according to a voltage of a QB-o node;
• an even pull-down unit decreasing the output voltage of the present stage in an even frame according to a voltage of a QB-e node;
• a third odd TFT connected to the QB-o node, a gate electrode and a drain electrode of the third odd TFT connected to each other and receiving an odd source voltage;
• and
• a third even TFT connected to the QB-e node, a gate electrode and a drain electrode of the third even TFT connected to each other and receiving an even source voltage.

A shift register stage of a driving circuit for a flat panel display device, comprising:

• a first thin-film transistor (TFT) having a gate and drain electrode both connected to a start signal terminal;
• a second TFT having a gate and drain electrode both connected to an odd source voltage terminal;
• a third TFT having a gate and drain electrode both connected to an even source voltage terminal;
• a fourth TFT connected between a clock terminal and an output node of the shift register stage, a source of the first TFT connected to a gate of the fourth TFT.