Sigma-delta modulator for PLL circuits

A PLL circuit comprising:

• a sigma-delta modulator for generating a modulation signal for modulating a frequency division ratio for a comparator/frequency divider of a PLL circuit, the sigma-delta modulator including:
• a plurality of series-connected integrators, each accumulating an input signal based on a clock signal and outputting an overflow signal when an accumulated value exceeds a predetermined value;
• a plurality of differentiators selectively connected to the plurality of integrators, each of the differentiators transferring an overflow signal of a corresponding one of the integrators;
• an adder for multiplying the overflow signals transferred from the plurality of differentiators by a predetermined coefficient and adding the products to generate the modulation signal;
• and
• a control circuit, connected between a first integrator of a final stage and a second integrator of a stage preceding the final stage, for providing an output signal of the second integrator to the first integrator in synchronization with a frequency-divided signal obtained by frequency-dividing the clock signal;
• and
• a comparator/frequency divider, connected to the sigma-delta modulator, for performing a fractional frequency division operation according to a modulation signal of the sigma-delta modulator.

A fractional-N PLL frequency synthesizer, comprising:

• a sigma-delta modulator for generating a modulation signal for modulating a frequency division ratio for a comparator/frequency divider of a PLL circuit, the sigma-delta modulator including:
• a plurality of series-connected integrators, each accumulating an input signal based on a clock signal and outputting an overflow signal when an accumulated value exceeds a predetermined value;
• a plurality of differentiators selectively connected to the plurality of integrators, each of the differentiators transferring an overflow signal of a corresponding one of the integrators;
• an adder for multiplying the overflow signals transferred from the plurality of differentiators by a predetermined coefficient and adding the products to generate the modulation signal;
• and
• a control circuit, connected between a first integrator of a final stage and a second integrator of a stage preceding the final stage, for providing an output signal of the second integrator to the first integrator in synchronization with a frequency-divided signal obtained by frequency-dividing the clock signal;
• a comparator/frequency divider, connected to the sigma-delta modulator, for performing a fractional frequency division operation in accordance with a modulation signal of the sigma-delta modulator and generating a comparison signal;
• a reference frequency divider for generating a reference signal;
• and
• a phase comparator, connected to the comparator/frequency divider and the reference frequency divider, for comparing the reference signal and the comparison signal and generating a phase comparison signal.