Differential front-end continuous-time sigma-delta ADC using chopper stabilisation

A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) with an input stage comprising:

• a first and a second differential input line which are operable to receive an analog input signal current;
• a multi-bit feedback current digital-to-analog converter (IDAC) which is operable to generate a multi-level feedback current depending on a feedback signal, the IDAC having a first output branch and a second output branch;
• an integrator having a first and a second differential input which is operable to integrate a difference of the current generated by the multi-bit IDAC and the input signal current on a continuous-time basis;
• a first biasing current source and a second biasing current source which are operable to bias the input stage in a mid-scale condition;
• a first summing node which connects to the first differential input line, the first differential input of the integrator and the first output branch;
• a second summing node which connects to the second differential input line, the second differential input of the integrator and the second output branch;
• and,
• a set of chopping switches which are operable to alternately connect the biasing current sources to the summing nodes in a first configuration, in which the first biasing current source connects to the first summing node and the second biasing current source connects to the second summing node and a second configuration, in which the first biasing current source connects to the second summing node and the second biasing current source connects to the first summing node.