Phase locked loop
AssigneeNokia Corporation
InventorPeter Beeson
Life of this patent
Estimating the term…
Abstract
A phase locked loop circuit, for providing an oscillating output signal at an output frequency, including: a reference counter; a loop counter; a phase detector having a first input coupled to the reference counter and a second input coupled to the loop counter; a voltage controlled oscillator having an input coupled to the output of the phase detector and an output for providing the oscillating output signal; a feedback loop coupling the output of the voltage controlled oscillator to the input of the loop counter; and delay circuitry, including a feedback loop, arranged to introduce a discrete delay into the output of the loop counter and/or the reference counter.
Claims38
A phase locked loop circuit, for providing an oscillating output signal at an output frequency, comprising:
- a reference counter;
- a loop counter;
- a phase detector having a first input coupled to the reference counter and a second input coupled to the loop counter;
- a voltage controlled oscillator having an input coupled to the output of the phase detector and an output for providing the oscillating output signal;
- a feedback loop coupling the output of the voltage controlled oscillator to the input of the loop counter;
- and
- delay circuitry, including a feedback loop, arranged to introduce a discrete delay into the output of the loop counter and/or the reference counter.
A method of changing the frequency of an oscillating output signal comprising the steps of:
- adapting the reference counter and/or the loop counter of a phase locked loop;
- and
- introducing a discrete delay into the output of the loop counter and/or the reference counter.
A frequency synthesiser, for providing an oscillating output signal at an output frequency, comprising:
- frequency compensation means arranged to maintain the output frequency;
- and
- feedback means arranged to vary discretely the phase of an input signal provided to the compensation means.
A phase locked loop circuit, for providing an oscillating output signal at an output frequency, comprising:
- a loop counter;
- a phase detector having a first input coupled to the reference counter and a second input coupled to the loop counter;
- a voltage controlled oscillator having an input coupled to the output of the phase detector and an output for providing the oscillating output signal;
- a feedback loop coupling the output of the voltage controlled oscillator to the input of the loop counter;
- and
- delay circuitry, including a feedback loop, arranged to introduce a discrete delay into the output of the loop counter.
A method of changing the frequency of an oscillating output signal comprising the steps of:
- adapting a loop counter of a phase locked loop;
- and
- using a feedback loop to introduce a discrete delay into the output of the loop counter.
A frequency synthesiser, for providing an oscillating output signal at an output frequency, comprising:
- frequency compensation means comprising:
- an input for receiving a first input signal;
- comparison means for comparing the first input signal and a second input signal;
- control means for controlling the output frequency in dependence upon the comparison;
- and a negative feedback loop for providing the second input signal;
- and feedback means arranged to vary discretely the phase of the first input signal and to vary continuously the phase of the first input signal.
A frequency synthesiser, for providing an oscillating output signal at an output frequency, comprising:
- frequency compensation means comprising:
- an input for receiving a first input signal;
- comparison means for comparing the first input signal and a second input signal;
- control means for controlling the output frequency in dependence upon the comparison;
- and a negative feedback loop for providing the second input signal;
- and feedback means arranged to vary discretely the phase of the second input signal and to vary continuously the phase delay of the second input signal.
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Dependencies are inferred from the claim text.