Low voltage CMOS differential amplifier
AssigneeMicron Technology, Inc.
InventorsSugato Mukherjee, Yangsung Joo
Life of this patent
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Abstract
A low voltage CMOS differential amplifier is provided. More specifically, there is provided a device comprising a differential pair coupled to a first tail current transistor and to a component wherein the first tail current transistor is configured to provide a tail current to the differential pair and the component is configured to provide a tail current to the differential pair when the first tail current transistor is operating in a triode region or in a cut-off region.
Claims28
A device comprising:
- a differential pair;
- a first transistor, being coupled to the differential pair, and configured to provide a current to the differential pair;
- and
- a component, being coupled to the differential pair, and configured to provide the current to the differential pair when the first transistor is operating in a triode region or in a cut-off region.
A device comprising a differential amplifier, wherein the differential amplifier comprises a fixed biased transistor coupled in parallel to a self-biased transistor and wherein the fixed biased transistor and the self-biased transistor are configured to provide a current to the differential amplifier.
A device comprising:
- a PMOS differential amplifier;
- and
- an NMOS differential amplifier, wherein the NMOS differential amplifier is coupled to the PMOS differential amplifier and wherein the device is configured to operate as an inverter when a supply voltage is below a predetermined threshold.
A method of operating a device comprising:
- providing a supply voltage to a differential amplifier;
- biasing a fixed biased transistor disposed on the differential amplifier;
- and
- providing a current to a differential pair within the differential amplifier, wherein the current is at least partially provided by the fixed biased transistor.
A system comprising:
- a processor;
- and
- a memory device operatively coupled to the processor, the memory device comprising:
- a differential pair, coupled to the current source;
- a current transistor, being coupled to the differential pair, and configured to provide a current to the differential pair;
- and
- a second current transistor, being coupled to the differential pair, and configured to provide the current to the differential pair when the first transistor is operating in a triode region.
A device comprising:
- a differential pair including a first transistor and a second transistor;
- a third transistor coupled to the first transistor and the second transistor and configured to provide a supply current to the first transistor and the second transistor;
- a component, being coupled to the first transistor and the second transistor and configured to provide the supply current to the first transistor and the second transistor when the third transistor is operating in a triode region or in a cut-off region.
Dependencies are inferred from the claim text.