Three-channel state-variable compressor circuit

A three channel state variable compressor circuit comprising:

• an all-pass state-variable filter having an input coupled to receive and process an IPS (input program signal) into a low frequency band signal, a middle frequency band signal and high frequency band Signal, the middle frequency band signal having an additional inversion stage with respect to the low-frequency and high frequency band signals,
• a first, second and third SDC (Scaled Detector Circuit), each SDC having an input coupled to receive a respective frequency band signal and an output, each SDC being characterized to buffer, rectify and filter its respective frequency band signal to form a control voltage at its output,
• a first second and third VCA (Voltage Control Amplifier), each VCA having a respective signal input coupled to a respective frequency band signal and a control voltage input coupled to a respective control voltage at its respective SDC output, each VCA being characterized to reduce its gain in response to an increase in the control voltage applied to its control voltage input and to provide a respective GCFRIPS (Gain Controlled Frequency Range Input Program Signal), and
• a summing circuit having a first second and third input, each input being coupled to receive a respective GCFRIPS, the summing amplifier adding the first, second and third GCFRIPS to provide a COS (Composite Operating Signal) at a Summing Circuit Output.

A three channel state variable compressor circuit comprising

• an all-pass state-variable filter having an input coupled to receive and process an IPS (input program signal), into three signals, each respective signal being limited to a respective frequency range, the three signals including:
• a HFRIPS (High Frequency Range Input Program Signal),
• an MFRIPS (Mid-Frequency Range Input Program Signal), and
• a LFRIPS (Low-Frequency Range Input Program Signal),
• a first, second and third VCA (Voltage Controlled Amplifier) circuit, each respective VCA having a signal input, a control signal input, and an output,
• a SDC (Scaled Detector Circuit) means for sampling, scaling, rectifying and filtering the HFRIPS (High Frequency Range Input Program Signal), the MFRIPS (Mid-Frequency Range Input Program Signal), and the LFRIPS (Low-Frequency Range Input Program Signal) to provide
• a respective HFRGCS (High-Frequency Range Gain Control Signal) to the first VCA control voltage input,
• an MFRGCS (Mid-Frequency Range Gain Control Signal) to the second VCA control voltage input, and
• a LFRGCS (Low-Frequency Range Gain Control Signal) to the third VCA control voltage input, the first second and third VCA (Voltage Control Amplifier), responding to their respective Gain Control Signals and respectively to the corresponding HFRIPS, the MFRIPS and the LFRIPS to provide
• a GCHFRIPS (Gain Controlled High-Frequency Range Input Program Signal),
• a GCMFRIPS (Gain Controlled Mid-Frequency Range Input Program Signal) and
• a GCLFRIPS (Gain Controlled Low-Frequency Range Input Program Signal),
• a summing circuit having a first second and third input, each respective summing circuit input being coupled to its corresponding VCA first, second and third output to add and provide the sum of the GCHFRIPS, the GCMFRIPS and the GCLFRIPS to provide a COS (Composite Operating Signal) at a Summing Circuit Output.

A combination three channel state variable compressor circuit and process comprising:

• an all-pass state-variable filter circuit having an input coupled to receive and process an IPS (input program signal), into three signal signals, each respective signal being limited to a respective frequency range, the three signals including:
• a HFRIPS (High Frequency Range Input Program Signal),
• an MFRIPS (Mid-Frequency Range Input Program Signal), and
• a LFRIPS (Low-Frequency Range Input Program Signal),
• an ADC (analog to digital converter) having an input coupled to receive, to sample and to convert the HFRIPS, the MFRIPS and the LFRIPS signals into a sequence of frames of DIPS (digitized input program signal) values, each frame of DIPS values comprising the sampled value of a digitized HFRIPS, MFRIPS and LFRIPS signal acquired at a frame sample from three streams of DFRIPS (Digital Frequency Range Input Program Signal values), each respective DFRIPS being limited to a respective frequency range,
• a first signal process or program, which, when executing in a digital signal processor, is operative for emulating a first, second and third SDC (Scaled Detector Circuit), each emulated SDC within the signal process having an input coupled to receive a respective HFRIPS, a MFRIPS or an LFRIPS, to scale, rectify and filter the HFRIPS, the MFRIPS and the LFRIPS and to provide a respective first, a second and a third stream of DRGCS (Digital Range Gain Control Signal) values,
• a second signal process or program, which, when executing in said digital signal processor, is operative for emulating a first second and third VCA (Voltage Control Amplifier), each emulated VCA within the signal process having a respective digital signal input coupled to receive a respective stream of DFRIPS values, a respective control digital signal input coupled to receive a respective stream of DRGCS values, and a respective output to provide a stream of respective frames of digitized first, second and third DGCFRIPS (Digital Gain Controlled Frequency Range Input Program Signal) values, and
• a third signal process or program, which, when executing in said digital signal processor, is operative for emulating a summing circuit having a first second and third digital input, each digital input being coupled to receive a respective stream of DGCFRIPS values, the signal process adding the first, second and third DGCFRIPS values in each sample set or frame to form a stream of DCOS (Digital Composite Operating Signal) values,
• a digital to analog converter for converting the stream of DCOS values into and analog COS (composite output signal).

A three channel state variable compressor process operating in a digital signal processor comprising:

• an ADC (analog to digital converter) having an input coupled to receive an IPS (input program signal) and characterized to provide a sequence of DIPS (digitized input program signal values), each DIPS characterizing the amplitude of the input program signal at a sample rate,
• a first digital signal process or program, which, when executing in said digital signal processor, is operative for emulating an all-pass state-variable filter which has an input coupled to receive and process DIPS into three streams of DFRIPS (Digital Frequency Range Input Program Signal values), each stream of respective DFRIPS being limited to a respective frequency range,
• a second signal process or program, which, when executing in said digital signal processor, is operative for emulating a first, second and third SDC (Scaled Detector Circuit), each emulated SDC having an input coupled to receive a respective stream of DFRIPS, to scale, rectify and filter the DFRIPS and to provide a respective first, a second and a third stream of DRGCS (Digital Range Gain Control Signal) values,
• a third signal process or program, which when executing in said digital signal processor, is operative for emulating a first second and third VCA (voltage Control Amplifier), each emulated VCA having a respective digital signal input coupled to receive a respective DFRIPS, a respective control digital signal input coupled to receive a respective DRGCS, and a respective output to provide stream of respective frames of digital first, second and third DGCFRIPS (Digital Gain Controlled Frequency Range Input Program Signal) values, and
• a fourth signal process or program, which, when executing in said digital signal processor, is operative for emulating a summing circuit having, a first second and third digital input, each digital input being coupled to receive a respective stream of DGCFRIPS values the a fourth signal process adding the first, second and third DGCFRIPS values in each set or frame to form a stream of DCOS (Digital Composite Operating Signal) values,
• a digital to analog converter for converting the stream of DCOS values into and analog COS (composite output signal).