Latch-based pulse generator
AssigneeSamsung Electronics Co., Ltd.
InventorsDo-Kyung Kim, Yong-Weon Jeon
Life of this patent
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Abstract
There is provided a pulse generator capable of generating a pulse with a reduced number of transistors that toggle in response to a clock signal, thereby reducing power consumption. The pulse generator includes a plurality of unit cells, wherein an nth unit cell (n is a natural number more than 2) generates a pulse in response to a divided-by-N clock signal (N is a natural number), a signal output from an (n−1)th unit cell and a signal output from an (n+1)th unit cell. The nth unit cell is reset or generates the pulse whose width is equivalent to the width of the clock signal, according to the logic level of the signal output from the n+1th unit cell.
Claims6
A pulse generator comprising:
- a first NAND gate that NANDs a first input signal and a second input signal;
- a first inverter that inverts a signal output from the first NAND gate;
- a second NAND gate that NANDs a divided-by-N clock signal and a signal output from the first inverter;
- a second inverter that inverts a signal output from the second NAND gate;
- and
- a latch that latches a reset signal and the signal output from the second NAND gate.
A pulse generator comprising:
- a first NAND gate that NANDs a first input signal and a second input signal input to a second input terminal;
- a first inverter that inverts a signal output from the first NAND gate;
- a second NAND gate that NANDs a divided-by-N clock signal input to a first input terminal and a signal output from the first inverter;
- a second inverter;
- a first transmission circuit that responds to a signal output from the second NAND gate and a signal output from the second inverter;
- a second transmission circuit that responds to the signal output from the second NAND gate and the signal output from the second inverter;
- a third NAND gate that NANDs a reset signal and a signal output from the shared node and outputs the result of NAND to a third output terminal;
- and
- a third inverter.
Dependencies are inferred from the claim text.