Modifying clock signals output by an integrated circuit
AssigneeInfineon Technologies AG
InventorBan Goh
Life of this patent
Estimating the term…
Abstract
An integrated circuit of the kind which transmits a clock-signal off-chip to a load (7) is provided with a load measurement circuit (4), which measures a load value indicative of the power being drawn from the IC by the clock output (5), and a comparison circuit (13), which compares the load value to a “high” load value (21) and a “low” load value (17). The integrated circuit stops transmitting the clock signal off-chip if the measured load value is above the “high” load value (21), indicating that the power drawn may be beyond the operational limits of the integrated circuit. Also, the integrated circuit stops transmitting the clock signal off-chip if the measured load value is below the “low” load value (17), indicating that the clock signal is unused.
Claims21
An integrated circuit comprising:
- a clock signal generation unit for generating a clock signal for transmission off the chip through a clock signal output pin;
- a load measurement circuit which measures a load value indicative of power being drawn from the integrated circuit from the clock signal output pin;
- and
- a comparison circuit for comparing the load value to one or more predetermined load thresholds and which is operative to prevent the clock signal from being transmitted through the clock signal output pin according to the result of the comparing.
An integrated circuit comprising:
- means for generating a clock signal for transmission off the chip through a clock signal output pin;
- means for measuring a load value indicative of power being drawn from the integrated circuit from the clock signal output pin;
- and
- means for comparing the load value to one or more predetermined load thresholds and for causing prevention of the clock signal from being transmitted through the clock signal output pin according to the result of the comparing.
A method of operating a semiconductor chip, the method comprising:
- generating a clock signal;
- driving the clock signal off of the chip;
- determining an amount of power being drawn from the clock signal;
- and
- disabling the driving of the clock signal off of the chip if the determined amount of power differs from a threshold criteria.
An integrated circuit comprising:
- a clock signal generation unit for generating a clock signal for transmission off the chip through a clock signal output pin;
- a load measurement circuit which measures a load value indicative of power being drawn from the integrated circuit from the clock signal output pin;
- and
- a comparison circuit for comparing the load value to a predetermined low threshold and a predetermined high threshold, the comparison circuit being arranged to prevent the clock signal from being transmitted through the clock signal output pin when the load value is above the high threshold or below the low threshold, the low and high thresholds being settable according to the integrated circuit operational limits.
Dependencies are inferred from the claim text.