Z-state circuit for delay-locked loops
OwnerSangbeom Parkinventor
Life of this patent
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Abstract
The four types of the Z-state circuits basically include a sensing gate, two stacked PMOS transistors, and a feedback line. The sensing gate senses a voltage at its input assuming no feedback is applied. Again, the corresponding output of two stacked PMOS transistors is assumed to be connected to the sensing input. Two stacked PMOS transistors generate a high impedance Z-state at its output according to the corresponding gate voltages. Therefore, the feedback line keeps sampling the output and feeding back the output voltage to the sensing input. Consequently, the feedback configuration provides the initial loop condition, which is affected by the midpoint voltage decided by the device aspect ratios of the sensing gate before normal operation starts.
Claims20
A Z-state circuit for making any delay-locked loop very efficient, comprising:
- a feedback line connected with the output and input of the Z-state circuit coupled to an output of a filter within a delay-locked loop;
- a sensing inverter for sensing a voltage at the output, comparing with the midpoint voltage decided by the device aspect ratios of the sensing inverter, and providing its output;
- a two-input CMOS NAND gate for being used as an enabling inverter with one input serving as an inverting power-down input and the other used as the logical input;
- and
- two stacked PMOS transistors for generating a high impedance Z-state at its output according to the corresponding gate voltages;
Dependencies are inferred from the claim text.