Delay locked loop using synchronous mirror delay

A delay locked loop comprising:

• a circuit configured to:
• receive a clock signal;
• divide the clock signal by two to provide a divided clock signal and an inverted divided clock signal;
• mirror with respect to a falling edge of the divided clock signal a fractional portion of a feedback delay remaining after dividing the feedback delay by a multiple of a cycle of the clock signal to provide a first signal;
• mirror with respect to a falling edge of the inverted divided clock signal the fractional portion of the feedback delay to provide a second signal;
• and
• provide a delayed clock signal in response to the first signal and the second signal.

A delay locked loop comprising:

• a first clock divider configured to receive a clock signal and divide the clock signal by two to provide a divided clock signal and an inverted divided clock signal;
• a first feedback delay configured to delay the clock signal to provide a first feedback signal;
• a first synchronous mirror delay configured to mirror the feedback signal with respect to a falling edge of the divided clock signal in response to a rising edge of the first feedback signal during a logic high phase of the divided clock signal to provide a first signal;
• a second synchronous mirror delay configured to mirror the feedback signal with respect to a falling edge of the inverted divided clock signal in response to a rising edge of the first feedback signal during a logic high phase of the inverted divided clock signal to provide a second signal;
• and
• a first merge circuit configured to provide a delayed clock signal in response to the first signal and the second signal.

A method for delaying a clock signal in a delay locked loop, the method comprising:

• receiving a clock signal;
• dividing the clock signal by two to provide a divided clock signal;
• and
• mirroring with respect to the divided clock signal a fractional portion of a feedback delay remaining after dividing the feedback delay by a multiple of a cycle of the clock signal to provide a first signal.

A memory circuit comprising:

• a delay locked loop configured to:
• receive a clock signal;
• divide the clock signal by two to provide a divided clock signal;
• and
• mirror with respect to the divided clock signal a fractional portion of a feedback delay remaining after dividing the feedback delay by a multiple of a cycle of the clock signal to provide a first signal;
• and
• a memory coupled to the delay locked loop.

A delay locked loop comprising:

• a circuit configured to:
• receive a clock signal;
• divide the clock signal by two to provide a divided clock signal;
• and
• mirror with respect to the divided clock signal a fractional portion of a feedback delay remaining after dividing the feedback delay by a multiple of a cycle of the clock signal to provide a first signal,
• wherein the fractional portion of the feedback delay is mirrored by mirroring a first selected feedback signal from a first set of at least three feedback signals, the first selected feedback signal having a rising edge the farthest away from a rising edge of the divided clock signal.

A delay locked loop comprising:

• a circuit configured to:
• receive a clock signal;
• divide the clock signal by two to provide a divided clock signal;
• delay the divided clock signal to provide a first delayed divided clock signal and a second delayed divided clock signal;
• delay the clock signal to provide a feedback signal;
• delay the feedback signal to provide a first delayed feedback signal and a second delayed feedback signal;
• select one of the feedback signal, the first delayed feedback signal, and the second delayed feedback signal based on a comparison between a rising edge of the divided clock signal, a rising edge of the first delayed divided clock signal, and a rising edge of the second delayed divided clock signal and a phase of the second delayed feedback signal;
• mirror with respect to the divided clock signal the selected one of the feedback signal, the first delayed feedback signal, and the second delayed feedback signal to provide a first signal;
• and
• delay the first signal based on the selected one of the feedback signal, the first delayed feedback signal, and the second delayed feedback signal to provide a second signal.

A delay locked loop comprising:

• a first clock divider configured to receive a clock signal and divide the clock signal by two to provide a divided clock signal and an inverted divided clock signal;
• a first divided clock signal delay circuit configured to delay the divided clock signal to provide a first delayed divided clock signal and a second delayed divided clock signal;
• a first feedback delay circuit configured to delay the clock signal to provide a first feedback signal, a second feedback signal, and a third feedback signal;
• a first detection circuit configured to select one of the first feedback signal, the second feedback signal, and the third feedback signal based on a phase of the third feedback signal with respect to a rising edge of the divided clock signal, a rising edge of the first delayed divided clock signal, and a rising edge of the second delayed divided clock signal;
• a first synchronous mirror delay configured to mirror the selected one of the first feedback signal, the second feedback signal, and the third feedback signal with respect to a falling edge of the divided clock signal in response to a rising edge of the selected one of the first feedback signal, the second feedback signal, and the third feedback signal during a logic high phase of the divided clock signal to provide a first signal;
• a second synchronous mirror delay configured to mirror the selected one of the first feedback signal, the second feedback signal, and the third feedback signal with respect to a falling edge of the inverted divided clock signal in response to a rising edge of the selected one of the first feedback signal, the second feedback signal, and the third feedback signal during a logic high phase of the inverted divided clock signal to provide a second signal;
• a first merge circuit configured to provide a third signal in response to the first signal and the second signal;
• and
• an output delay configured to delay the third signal based on the selected one of the first feedback signal, the second feedback signal, and the third feedback signal to provide a delayed clock signal.

A method for delaying a clock signal in a delay locked loop, the method comprising:

• receiving a clock signal;
• dividing the clock signal by two to provide a divided clock signal;
• delaying the divided clock signal to provide a first delayed divided clock signal and a second delayed divided clock signal;
• delaying the clock signal to provide a feedback signal;
• delaying the feedback signal to provide a first delayed feedback signal and a second delayed feedback signal;
• selecting one of the feedback signal, the first delayed feedback signal, and the second delayed feedback signal based on a comparison between a rising edge of the divided clock signal, a rising edge of the first delayed divided clock signal, and a rising edge of the second delayed divided clock signal and a phase of the second delayed feedback signal;
• mirroring with respect to the divided clock signal the selected one of the feedback signal, the first delayed feedback signal, and the second delayed feedback signal to provide a first signal;
• and
• delaying the first signal based on the selected one of the feedback signal, the first delayed feedback signal, and the second delayed feedback signal to provide a second signal.

A delay locked loop comprising:

• means for receiving a clock signal;
• means for dividing the clock signal by two to provide a divided clock signal;
• and
• means for mirroring with respect to the divided clock signal a fractional portion of a feedback delay remaining after dividing the feedback delay by a multiple of a cycle of the clock signal to provide a first signal.