Phase locked loop having enhanced locking characteristics

A phase locked loop device receiving an external signal input from an external source and generating an internal signal, the device comprising:

• a phase detector receiving the external signal and a fed back internal signal and detecting a phase difference between the external and internal signals;
• a charge pump generating a pumping signal in response to an output signal of the phase detector;
• and
• a voltage controlled oscillator generating the internal signal in response to the pumping signal, and decreasing electric current consumed at an output terminal of the voltage controlled oscillator when a frequency of the external signal is higher than that of the internal signal and increasing the electric current consumed at the output terminal of the voltage controlled oscillator when the frequency of the external signal is lower than that of the internal signal.

A phase locked loop device receiving an external clock signal input from an external source and generating an internal clock signal, the device comprising:

• a phase detector receiving the external clock signal and a fed back internal clock signal and detecting a phase difference between the external and internal clock signals;
• a charge pump generating a pumping signal in response to an output signal of the phase detector;
• and
• a voltage controlled oscillator receiving the pumping signal and generating the internal clock signal in response to the pumping signal,
• wherein the voltage-controlled oscillator comprises
• a control signal generator receiving the pumping signal, and generating a deactivated variable control signal when a frequency of the external clock signal is higher than that of the internal clock signal and generating an activated variable control signal when the frequency of the external clock signal is lower than that of the internal clock signal;
• an inverting unit receiving the fed back internal clock signal and outputting the internal clock signal;
• a load capacitor connected to an output terminal of the inverting unit in parallel;
• and
• a MOS transistor connected to the load capacitor in series, activated when the variable control signal is active, and deactivated when the variable control signal is inactive.

A phase locked loop device receiving an external signal input from an external source and generating an internal signal, the device comprising:

• a phase detector receiving the external signal and a fed back internal signal and detecting a phase difference between the external and internal signals;
• a charge pump receiving an output signal of the phase detector and generating an up-pumping signal when a frequency of the external signal is higher than that of the internal signal and generating a down-pumping signal when the frequency of the external signal is lower than that of the internal signal;
• and
• a voltage controlled oscillator comprising a control signal generator, which receives the up-pumping signal and the down-pumping signal and generates first and second control signals activated when the up-pumping signal is active and a variable control signal activated when the down-pumping signal is active, and an internal signal generator, which receives the first and second control signals and the variable control signal, generates the internal signal, decreases electric current consumed at an output terminal of the internal signal generator when the first and second control signals are active and the variable control signal is inactive, and increases the electric current consumed at the output terminal of the internal signal generator when the first and second control signals are inactive and the variable control signal is active.