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US 2006/0139071 A1Published application
Power-on-reset circuit based on the threshold levels and quadratic I-V behavior of MOS transistors
AssigneeMicron Technology, Inc.
InventorAlf Olsen
Life of this patent
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Abstract
A system and method for providing a clock-independent reset signal based on supply voltage threshold levels is described. The trip points or predefined voltage levels where the power-on-reset circuit behavior reverses (which controls the reset signal) is determined by the dimensions of the transistors selected for the voltage dividers. The system and method described allows for a clock-independent stable power-up phase while consuming a very small area of a circuit board and, in particular, on integrated circuits.
Claims21
1-59. (canceled)
A processor system comprising:
- a processor;
- and
- a clock-independent power-on-reset circuit coupled to said processor, said clock-independent power-on-reset circuit comprising:
- a first voltage divider connected to a supply voltage;
- a second voltage divider connected to said supply voltage;
- an amplifier coupled to said first and second voltage dividers, wherein said amplifier is a high gain amplifier in an open loop configuration and includes a differential stage having an output coupled to an even plurality of coupled asymmetrical inverters in addition to a coupled pair of asymmetrical inverters of said amplifier;
- a feedback circuit for feeding back an output of the amplifier to said input of the amplifier;
- and
- an even plurality of coupled asymmetrical inverters in addition to the coupled pair of asymmetrical inverters of said amplifier.
6 more elements
A processor system comprising:
- a processor;
- an integrated circuit coupled to said processor;
- and
- a clock-independent power-on-reset circuit coupled to said integrated circuit, said clock-independent power-on-reset circuit comprising:
- a first voltage divider connected to a supply voltage, said first voltage divider comprising a pair of high threshold short NMOS transistors and a resistor;
- a second voltage divider connected to said supply voltage;
- an amplifier coupled to said first and second voltage dividers, wherein said amplifier is a high gain amplifier in an open loop configuration and includes a differential stage having an output coupled to a first one of a coupled pair of asymmetrical inverters, wherein said high gain amplifier in open loop mode operates as a comparator;
- and
- a feedback circuit for feeding back an output of the amplifier to an input of the amplifier.
6 more elements
A system comprising:
- an integrated circuit;
- and
- a power-on-reset circuit connected to the integrated circuit, said power-on reset circuit comprising:
- a first voltage divider connected to a supply voltage, wherein the first voltage divider is an NMOS voltage divider;
- a second voltage divider connected to said supply voltage;
- an open loop mode high gain amplifier having non-inverting and inverting inputs for receiving outputs from said first and second voltage dividers respectively, said open loop mode high gain amplifier further comprises a differential stage, wherein said differential stage is coupled to said first voltage divider and further coupled to said second voltage divider, and a pair of coupled asymmetrical inverters;
- a feedback circuit for feeding back an output signal to said non-inverting input of said open loop mode amplifier, wherein said feedback circuit provides hysteresis to stabilize said high gain open loop mode amplifier;
- and
- an even plurality of coupled asymmetrical inverters in addition to the pair of coupled asymmetrical inverters of said amplifier.
6 more elements
A processor system comprising:
- a processor;
- and
- a clock-independent power-on-reset circuit coupled to said processor, said clock-independent power-on-reset circuit comprising:
- a NMOS voltage divider connected to a supply voltage;
- a PMOS voltage divider connected to said supply voltage;
- an open loop mode high gain amplifier having non-inverting and inverting inputs for receiving outputs from said NMOS and PMOS voltage dividers respectively, said amplifier comprising asymmetrical inverters;
- and
- a feedback circuit for feeding back an output signal to said non-inverting input of said open loop mode amplifier;
- and
- an even plurality of coupled asymmetrical inverters in addition to the coupled pair of asymmetrical inverters of said amplifier.
7 more elements
Dependencies are inferred from the claim text.