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US 2006/0139061 A1Published application
Protected set dominant latch
OwnerSteve Curtis, Grant McFarland +1inventors
InventorsSteve Curtis, Grant McFarland, Brian Flanagan
Life of this patent
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Abstract
In some embodiments, a set dominant latch with an input node and a state node is provided the circuit includes at least one driver gate coupled to the state node and to the input node to provide a driven output of the state node. Other embodiments are disclosed and/or otherwise claimed.
Claims22
A chip, comprising:
- (a) a set dominant latch circuit having an input node and a state node;
- and
- (b) at least one driver gate coupled to the state node and the input node to provide a driven output of the state node.
A chip, comprising:
- (a) a latch in a domino section, the latch having an input node and a state node and being capable of latching a value during an evaluate phase and being set upon receiving an active input when out of the evaluate phase when being operated;
- and
- (b) at least one driver gate coupled to the state node and the input node to provide a driven output of the state node.
A system, comprising:
- (a) a microprocessor having a domino circuit comprising:
- (i) a set dominant latch circuit having an input node and a state node, and
- (ii) at least one driver gate coupled to the state node and the input node to provide a driven output of the state node;
- and
- (b) a wireless interface component communicatively linked to the microprocessor.
2 more elements
Dependencies are inferred from the claim text.