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US 2006/0139057 A1Published application
Structured integrated circuit device
AssigneeeASIC Corporation
InventorsZvi Or-Bach, Ze'ev Wurman, Adam Levinthal
Life of this patent
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Abstract
A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
Claims13
A semiconductor device comprising:
- a multiplicity of logic cells;
- a multiplicity of decoders;
- and
- metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof;
- wherein
- said logic cells include at least one look up table and at least one multiplexer;
- said customized interconnect is customized by a custom via layer;
- and
- said at least two of said decoders are interconnected with at least one of said logic cells for use as a RAM in one mode, and wherein said decoders are used to program said logic cells for use as a RAM and to program at least one other said logic cell.
6 more elements
A semiconductor device comprising:
- a logic array, said logic array including a multiplicity of logic cells;
- a multiplicity of phase lock loop circuits;
- metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof;
- and
- a customizable clock distribution structure, wherein said customizable clock distribution structure includes at least one connection from one of said logic cells to at least one of said phase lock loop circuits to send a clock signal from said logic cell to said phase lock loop circuit, and wherein said customized interconnect and said customized clock distribution structure are customized by a single custom via layer.
2 more elements
A semiconductor device comprising:
- a logic array, said logic array including a multiplicity of logic cells;
- at least one built-in microprocessor;
- at least one block of RAM;
- at least one ROM;
- and
- metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof,
- wherein said customized interconnect is customized by a single custom via layer, and wherein said microprocessor is adapted to program said logic cells to perform specified logic functions in one mode by transferring external configuration data through said RAM into said logic cells and in another mode by transferring configuration data from said ROM into said logic cells, said mode to be determined by accessing data external to said semiconductor device.
4 more elements
A semiconductor device comprising:
- a logic array, said logic array including blocks of logic cells;
- metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof;
- wherein said customized interconnect is customized by a single custom via layer and wherein said interconnect includes at least one interconnection to distribute power to at least one of said blocks of logic cells.
A semiconductor device comprising:
- a logic array, said logic array including a multiplicity of logic cells;
- said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer;
- and
- a multiplicity of device customized I/O cells, wherein said customized I/O cells are customized by said custom via layer, and wherein said customization includes holding a logic state within said I/O cell.
1 more element
A semiconductor device comprising:
- a logic array, said logic array including a multiplicity of logic cells;
- said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer;
- and
- a multiplicity of device customized I/O cells, wherein said customized I/O cells are customized by said custom via layer, and wherein said customization includes a termination resistor within said I/O cell.
1 more element
Dependencies are inferred from the claim text.