Variable impedence output buffer

A level shifter for selectively converting a semiconductor device for operation at a variety of supply voltage ranges, the level shifter comprising:

• a first and a second PMOS transistor coupled in series with a first NMOS transistor between a power supply node and a ground node, wherein gates of the first NMOS transistor and the second PMOS transistor are coupled to an input of the level shifter;
• a second NMOS transistor coupled in parallel with the first NMOS transistor, wherein the second NMOS transistor is coupled between a gate of a third PMOS transistor and the ground node and wherein a gate of the second NMOS transistor is selectively coupled to the input of the level shifter by a first programmable interconnect;
• a second programmable interconnect coupled between the gate of the second NMOS transistor and the ground node;
• a fourth PMOS transistor coupled in series with the third PMOS transistor and a third NMOS transistor between the power supply node and the ground node, wherein gates of the third NMOS transistor and the fourth PMOS transistor are coupled to a complement of the input of the level shifter, which in turn is selectively coupled to a gate of a fourth NMOS transistor by a third programmable interconnect;
• a fourth NMOS transistor coupled in parallel with the third NMOS transistor, wherein the fourth NMOS transistor is coupled between a gate of the first PMOS transistor and the ground node and wherein a gate of the fourth NMOS transistor is selectively coupled to the complement of the input of the level shifter by a third programmable interconnect;
• and
• a fourth programmable interconnect coupled between the gate of the fourth NMOS transistor and the ground node.

A level shifter for selectively converting a semiconductor device for operation at a variety of supply voltage ranges, the level shifter comprising:

• a first PMOS transistor having a gate, a first source/drain region and a second source/drain region, wherein the first source/drain region is coupled to a power supply node;
• a second PMOS transistor having a gate, a first source/drain region and a second source/drain region, wherein the first source/drain region of the second PMOS transistor is coupled to the second source/drain region of the first PMOS transistor and wherein the gate of the second PMOS transistor is coupled to receive an input signal;
• a first NMOS transistor having a gate, a first source/drain region and a second source/drain region, wherein the gate of the first NMOS transistor is coupled to receive the input signal, wherein the first source/drain region of the first NMOS transistor is coupled to the second source/drain region of the second PMOS transistor, and wherein the second source/drain region of the first NMOS transistor is coupled to a ground node;
• a second NMOS transistor having a gate, a first source/drain region and a second source/drain region, wherein the first source/drain region of the second NMOS transistor is coupled to the first source/drain region of the first NMOS transistor and to an output node of the level shifter, and wherein the second source/drain region of the second NMOS transistor is coupled to the second source/drain region of the first NMOS transistor;
• a third PMOS transistor having a gate, a first source/drain region and a fifth source/drain region, wherein the first source/drain region of the third PMOS transistor is coupled to the power supply node and wherein the gate of the third PMOS transistor is coupled to the output node of the level shifter;
• a fourth PMOS transistor having a gate, a first source/drain region and a second source/drain region, wherein the first source/drain region of the fourth PMOS transistor is coupled to the second source/drain region of the third PMOS transistor and wherein the gate of the fourth PMOS transistor is coupled to receive a complement of the input signal;
• a third NMOS transistor having a gate, a first source/drain region and a second source/drain region, wherein the gate of the third NMOS transistor is coupled to receive the complement of the input signal, wherein the first source/drain region of the third NMOS transistor is coupled to the second source/drain region of the fourth PMOS transistor and to the gate of the first PMOS transistor, and wherein the second source/drain region of the third NMOS is coupled to the ground node;
• a fourth NMOS transistor having a gate, a first source/drain region and a second source/drain region, wherein the first source/drain region of the fourth NMOS transistor is coupled to the first source/drain region of the third NMOS transistor and wherein the second source/drain region of the fourth NMOS transistor is coupled to the first source/drain region of the third NMOS transistor;
• a first programmable interconnect coupled between the second source/drain region of the second NMOS transistor and the gate of the second NMOS transistor;
• a second programmable interconnect coupled between the gate of the first NMOS transistor and the gate of the second NMOS transistor;
• a third programmable interconnect coupled between the second source/drain region of the fourth NMOS transistor and the gate of the fourth NMOS transistor;
• and
• a fourth programmable interconnect coupled between the gate of the third NMOS transistor and the gate of the fourth NMOS transistor.

A memory device, comprising:

• an array of memory cells;
• an input/output circuit for providing bi-directional communications and containing an output buffer circuit coupled to the array of memory cells, wherein the output buffer circuit comprises:
• a driver stage comprising one or more drive transistors coupled to receive a signal representative of a data value of a memory cell of the array;
• a pre-driver stage coupled to the driver stage;
• and
• a feedback circuit to dynamically control output buffer impedance in response to a load condition;
• wherein the feedback circuit comprises cascode-connected drive transistors.

A memory device, comprising:

• an array of memory cells;
• an input/output circuit for providing bi-directional communications and containing an output buffer circuit coupled to the array of memory cells, wherein the output buffer circuit comprises:
• a pull-up driver coupled between a power supply node and an output node;
• a pull-down driver coupled between a ground node and the output node;
• a pull-up pre-driver coupled to the pull-up driver;
• and
• a pull-down pre-driver coupled to the pull-down driver;
• wherein the pull-up and pull-down drivers each comprise a plurality of cascode-connected drive transistors;
• and
• wherein a gate of at least one of the cascode-connected drive transistors in each driver is coupled to the output node.

A memory device, comprising:

• an array of memory cells;
• an input/output circuit for providing bi-directional communications and containing an output buffer circuit coupled to the array of memory cells, wherein the output buffer circuit comprises:
• a pull-down output driver stage, comprising:
• a first NMOS pull-down transistor coupled between a ground node and an output pad, and
• second and third NMOS pull-down transistors coupled in cascode between the ground node and the output pad, the second NMOS pull-down transistor comprising a gate coupled to a gate of the first NMOS pull-down transistor;
• a pull-up output driver stage, comprising:
• a first PMOS pull-up transistor coupled between a power supply node and the output pad, and
• second and third PMOS pull-up transistors coupled in cascode between the power supply node and the output pad, the second PMOS pull-up transistor comprising a gate coupled to a gate of the first PMOS pull-up transistor and the third PMOS pull-up transistor comprising a gate coupled to a gate of the third NMOS pull-down transistor;
• a pull-up pre-driver stage coupled to the gate of the second PMOS pull-up transistor;
• and
• a pull-down pre-driver stage coupled to the gate of the second NMOS pull-down transistor.

A memory device, comprising:

• an array of memory cells;
• an input/output circuit for providing bi-directional communications and containing an output buffer circuit coupled to the array of memory cells, wherein the output buffer circuit comprises:
• a pull-up driver stage coupled to receive a first signal for coupling an output node of the output buffer to a supply potential node in response to the first signal having a first logic level and for presenting a high impedance to the output node in response to the first signal having a second logic level;
• and
• a pull-down driver stage coupled to receive a second signal for coupling the output node to a ground potential node in response to the second signal having the second logic level and for presenting a high impedance to the output node in response to the second signal having a first logic level;
• wherein the pull-up driver stage comprises at least two cascode-connected transistors coupled between the supply potential node and the output node with at least one of its cascode-connected transistors coupled to receive the first signal on its gate and at least one of its cascode-connected transistors having its gate coupled to the output node;
• and
• wherein the pull-down driver stage comprises at least two cascode-connected transistors coupled between the ground potential node and the output node with at least one of its cascode-connected transistors coupled to receive the second signal on its gate and at least one of its cascode-connected transistors having its gate coupled to the output node.

A memory device, comprising:

• an array of memory cells;
• an input/output circuit for providing bi-directional communications and containing an output buffer circuit coupled to the array of memory cells, wherein the output buffer circuit comprises:
• a pull-up pre-driver section coupled to receive a first signal indicative of a data value of a memory cell of the array;
• a pull-down pre-driver section coupled to receive a second signal indicative of the data value of the memory cell of the array, wherein the first signal and the second signal are generally of the same logic level;
• a pull-up driver stage coupled to receive an output signal from the pull-up pre-driver section for coupling an output node of the output buffer circuit to a supply potential node in response to the first signal having a first logic level and for presenting a high impedance to the output node of the output buffer circuit in response to the first signal having a second logic level;
• and
• a pull-down driver stage coupled to receive an output signal from the pull-down pre-driver section for coupling the output node of the output buffer circuit to a ground potential node in response to the second signal having the second logic level and for presenting a high impedance to the output node of the output buffer circuit in response to the second signal having a first logic level;
• wherein each driver stage comprises feedback circuitry to dynamically control an impedance of the output buffer in response to a load condition between the output buffer and the processor.