Planar view TEM sample preparation from circuit layer structures
AssigneeSystems on Silicon Manufacturing Co. Pte. Ltd.
InventorsWen Zhang, Siew Oh
Life of this patent
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Abstract
A method of preparing a planar view TEM sample of a planar portion of a circuit layer structure, the method comprising polishing the circuit layer structure until a cross-sectional polishing face of the circuit structure has substantially reached a first side face of the planar portion; forming a trench structure in the cross-sectional polishing face such that top and bottom faces of the planar portion are exposed; and performing a cut along the top and bottom faces of the planar region to free the planar view TEM sample.
Claims10
A method of preparing a planar view TEM sample of a planar portion of a circuit layer structure, the method comprising
- polishing the circuit layer structure until a cross-sectional polishing face of the circuit structure has substantially reached a first side face of the planar portion;
- forming a trench structure in the cross-sectional polishing face such that top and bottom faces of the planar portion are exposed;
- and
- performing a cut along the top and bottom faces of the planar region to free the planar view TEM sample.
Dependencies are inferred from the claim text.