Microelectronic package having stacked semiconductor devices and a process for its fabrication

Abstract

A packaged microelectronic device having a first and second electrically interconnected microelectronic elements and a method for its manufacture. Conductive posts extend from one major surface of the first microelectronic element. The first microelectronic element is electrically interconnected to the second microelectronic element via the conductive posts. The first microelectronic element preferably has an interposer element from which the conductive posts extend. The second microelectronic element is interconnected to the interposer element via contacts on the second microelectronic element via the conductive posts. The so interconnected microelectronic elements have coordinated functionality, such as a programmable logic device wherein one microelectronic element is a field programmable gate array and the other microelectronic element is a memory device. The packaged microelectronic device is formed by using a transfer substrate to transfer solder masses onto at least some of the conductive posts extending from the first major surface of the first microelectronic element or contacts on the second microelectronic element. The solder masses are then used to electrically interconnect the conductive posts with the contacts disposed on the surface of the second microelectronic element.

Dependencies are inferred from the claim text.