Capacitor pad network to manage equivalent series resistance

A method comprising:

• fabricating a first conductive plane comprising a first conductive trace;
• fabricating a first dielectric material upon the first conductive plane;
• fabricating a first microvia, a second microvia and a third microvia within the first dielectric material, the first microvia and the second microvia being coupled to the first conductive trace;
• fabricating a second conductive plane above the first dielectric material, the second conductive plane comprising a second conductive trace and a third conductive trace, the second conductive trace being coupled to the first microvia and the third conductive trace being coupled to the second microvia and to the third microvia;
• fabricating a second dielectric material upon the second conductive plane;
• fabricating a fourth microvia within the second dielectric material, the fourth microvia being coupled to the second conductive trace;
• and
• fabricating a first conductive pad coupled to the fourth microvia.

A system comprising:

• a microprocessor;
• an integrated circuit package coupled to the microprocessor, the integrated circuit package comprising:
• a first conductive pad;
• a first conductive plane;
• first dielectric material disposed between the first conductive plane and the first conductive pad;
• a second conductive plane;
• second dielectric material disposed between the first conductive plane and the second conductive plane;
• and
• a first conductive network comprising:
• a first microvia within the first dielectric material and coupled to the first conductive pad;
• a first conductive trace within the first conductive plane and coupled to the first microvia;
• a second microvia within the second dielectric material and coupled to the first conductive trace;
• a second conductive trace within the second conductive plane and coupled to the second microvia;
• a third microvia within the second dielectric material and coupled to the second conductive trace;
• a third conductive trace within the first conductive plane and coupled to the third microvia;
• and
• a fourth microvia within the second dielectric material and coupled to the third conductive trace.