Power metal oxide semiconductor transistor layout with lower output resistance and high current limit
AssigneeRichtek Technology Corporation
InventorsHung-Der Su, Chun-Yen Huang, Chung-Lung Pai, Jing-Meng Liu
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Abstract
A power metal oxide semiconductor transistor layout is disclosed. The power metal oxide semiconductor transistor layout uses network of conductive lead line as a connection or a network connection to connect source and drain regions thereby achieves advantages of a high uniformity of current, low Rds_on, much less power loss, an actual line density two times larger than that of conventional layouts and a strengthened resistance to electron migration.
Claims14
A power metal oxide semiconductor transistor layout comprising:
- a gate electrode with a lattice pattern on a substrate having a first area and a second area;
- a plurality of source regions laid in said lattice pattern;
- a plurality of drain regions laid in said lattice pattern, each said source region is laid to be surrounded by said drain regions;
- a first network of conductive lead line connecting said source regions on said first region;
- a second conductive plane connecting said drain regions on said first region;
- a third network of conductive lead line connecting said drain regions on said second region;
- and
- a fourth conductive plane connecting said source regions on said second region, said first network of conductive lead line connects said fourth conductive plane, and said second conductive plane connects said third network of conductive lead line.
A power metal oxide semiconductor transistor layout comprising:
- a gate electrode with a strip grating pattern on a substrate having a first area and a second area;
- a plurality of source regions laid in said strip grating pattern;
- a plurality of drain regions laid in said strip grating pattern, each said drain region is surrounded by said source regions;
- a first network of conductive lead line connecting said source regions on said first region;
- a second conductive plane connecting said drain regions on said first region;
- a third network of conductive lead line connecting said drain regions on said second region;
- and
- a fourth conductive plane connecting said source regions on said second region, said first network of conductive lead line connects said fourth conductive plane, and said second conductive plane connects said third network of conductive lead line.
Dependencies are inferred from the claim text.