Nand flash memory device
AssigneeHynix Semiconductor Inc.
InventorsHee Park, Keon Shim, Jong Leem
Life of this patent
Estimating the term…
Abstract
A memory device capable of enlarging an interval between a source selection transistor and a memory cell adjacent to the source selection transistor, enlarging an interval between a drain selection transistor and a memory cell adjacent to the drain selection transistor, or enlarging the intervals between the source selection transistor and the memory cell adjacent to the source selection transistor and between the drain selection transistor and the memory cell adjacent to the drain selection transistor, prevents the memory cell adjacent to the source or drain selection transistor from being degraded in programming speed due to program disturbance.
Claims12
A non-volatile memory device comprising:
- a drain selection transistor coupled to a bitline;
- a source selection transistor coupled to a source line;
- and
- a plurality of memory cells coupled in series between the drain selection transistor and the source selection transistors, the memory cells including at least first, second, and third memory cells, the first memory cell being most proximate to the source selection transistor of the plurality of memory cells,
- wherein the source selection transistor and the first memory cell are separated by a first distance, and the second and third memory cells are separated by a second distance.
A non-volatile memory device comprising:
- a drain selection transistor coupled to a bitline;
- a source selection transistor coupled to a source line;
- and
- a plurality of memory cells coupled in series between the drain selection transistor and the source selection transistors, the memory cells including at least first, second, third, and fourth memory cells, the first memory cell being most proximate to the drain selection transistor of the plurality of memory cells,
- wherein the drain selection transistor and the first memory cell are separated by a first distance, and the second and third memory cells are separated by a second distance.
A non-volatile memory device comprising:
- a drain selection transistor coupled to a bitline;
- a source selection transistor coupled to a source line;
- and
- a plurality of memory cells coupled in series between the drain selection transistor and the source selection transistors, the memory cells including at least first, second, third, and fourth memory cells, the first memory cell being most proximate to the source selection transistor of the plurality of memory cells, the fourth memory cells being most proximate to the drain selection transistor of the plurality of memory cells,
- wherein the source selection transistor and the first memory cell are separated by a first distance, and the second and third memory cells are separated by a second distance, and the fourth memory cell and the drain selection transistor are separated by a third distance,
- wherein the first, second, and third distances are all different.
A NAND flash memory device comprising:
- a drain selection transistor coupled to a bitline and provided on a semiconductor substrate;
- a source selection transistor coupled to a source line and provided on the substrate;
- and
- a plurality of memory cells coupled in series between the drain selection transistor and the source selection transistors and provided on the substrate, the memory cells including at least first, second, and third memory cells, the first memory cell being most proximate to the source selection transistor of the plurality of memory cells,
- wherein a trench is formed in the substrate at an area between the source selection transistor and the first memory cell to increase an effective channel length within a restricted area to be greater than an effective channel length of the first and second memory cells.
Dependencies are inferred from the claim text.