Semiconductor memory device and method of fabricating the same
AssigneeKabushiki Kaisha Toshiba
InventorMutsuo Morikado
Life of this patent
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Abstract
A semiconductor memory device includes: a semiconductor device base having an insulating substrate and a semiconductor layer overlying it; a cell array formed on the semiconductor device base with memory cells disposed in such a manner that each of source and drain regions is shared by adjacent two memory cells arranged in a direction, the memory cell having an electrically floating channel body to store data defined by a carrier accumulation state of the channel body; and silicide films formed on the source and drain regions of the memory cell, wherein the memory cell is formed in such a state that at least a part of at least one of source and drain regions is lessened in width in comparison with the cannel region.
Claims18
A semiconductor memory device comprising:
- a semiconductor device base having an insulating substrate and a semiconductor layer overlying it;
- a cell array formed on said semiconductor device base with memory cells disposed in such a manner that each of source and drain regions is shared by adjacent two memory cells arranged in a direction, said memory cell having an electrically floating channel body to store data defined by a carrier accumulation state of the channel body;
- and
- silicide films formed on the source and drain regions of said memory cell, wherein
- said memory cell is formed in such a state that at least a part of at least one of source and drain regions is lessened in width in comparison with the cannel region.
A semiconductor memory device comprising:
- a semiconductor device base having an insulating substrate and a semiconductor layer overlying it, a plurality of device formation regions being defined on semiconductor device base, first semiconductor areas and second semiconductor areas being alternately arranged at a certain pitch in each the device formation region, the second semiconductor area having a width smaller than that of the first semiconductor area;
- a cell array formed on said semiconductor device base with memory cells disposed in such a manner that adjacent two memory cells share source and drain regions, said memory cell having an electrically floating channel body and a gate electrode to store data defined by a carrier accumulation state of the channel body, the gate electrode being formed as crossing above the first semiconductor area to continue as a word line, at least a part of at least one of the source and drain regions being formed in the second semiconductor area;
- and
- silicide films formed on the source and drain regions of said memory cells.
A method of fabricating a semiconductor memory device comprising:
- forming a plurality of device formation regions on a semiconductor device base having an insulating substrate and a semiconductor layer overlying it, each device formation region being defined in the semiconductor layer in such a state that first semiconductor areas and second semiconductor areas are alternately arranged at a certain pitch, the second semiconductor area having a width smaller than that of the first semiconductor area;
- forming gate electrodes of memory cells on the first semiconductor areas in each device formation regions of said semiconductor device base;
- forming source and drain regions of the memory cells in each device formation regions of said semiconductor device base in such a state that each of the source and drain regions is shared by two memory cells disposed adjacent in each device formation region, at least one of the source and drain regions being formed in the second semiconductor area;
- and
- forming silicide films on the top surfaces of the gate electrodes and source drain regions.
Dependencies are inferred from the claim text.