Nonplanar transistors with metal gate electrodes

A CMOS integrated circuit comprising:

• a p type nonplanar semiconductor device comprising a gate electrode formed from a first film stack formed over and around an n type semiconductor body defining the channel region, said channel region having a first doping concentration and a pair of p type source/drain regions on opposite sides of said gate electrode, said pair of source/drain regions comprising a source/drain extension region and a source/drain contact region;
• an n type nonplanar semiconductor device a gate electrode formed from said first film stack formed over and around a p type semiconductor body defining a channel region having a p type conductivity of the first concentration and a pair of n type source/drain regions on opposite sides of said gate electrode, said pair of n type source/drain regions comprising source/drain extension region and a source/drain contact region;
• and
• wherein the doping of said n type source/drain extension regions and said p type channel region of said n type nonplanar semiconductor device and said doping of said p type source/drain extension regions and said n type channel region of said PMOS device create an 0.9-1.1 eV difference in the threshold voltage of said gate electrode of said p type semiconductor device and said gate electrode of said n type semiconductor device.

A method of forming a semiconductor device comprising:

• forming a sacrificial gate electrode material and a hard mask material over a semiconductor body;
• patterning said sacrificial gate electrode material and said hard mask material into a hard mask and a sacrificial gate electrode;
• forming a dielectric layer over and around said sacrificial gate electrode and said hard mask;
• planarizing said dielectric layer until said hard mask is exposed and said dielectric layer is substantially planar with the top surface of said hard mask;
• etching away said hard mask to reveal said sacrificial gate electrode;
• etching away said sacrificial gate electrode to form an opening in said dielectric layer to expose said channel region of said semiconductor body;
• depositing a gate dielectric layer over and around said channel region of said semiconductor body in said opening and on said top surface of said planarized interlayer dielectric;
• blanket depositing a gate electrode material on said gate dielectric layer in said opening and on said gate dielectric layer on said dielectric layer;
• and
• polishing said gate electrode material on said gate dielectric layer until said gate electrode material and said gate dielectric layer are completely removed from the top surface of said dielectric layer to form a gate electrode and a gate dielectric layer.

A method of forming a metal oxide gate dielectric layer comprising:

• exposing a silicon surface to a solution which makes said silicon surface hydrophilic;
• exposing said hydrophilic silicon surface to a precursor comprising a metal halide;
• and
• forming a metal oxide dielectric layer by reacting said metal halide with said hydrophilic surface.

A method of forming a high dielectric constant film on a silicon surface comprising:

• removing a silicon oxide film from a silicon surface with an aqueous HF solution to generate a hydrophobic silicon hydride surface;
• treating said hydrophobic silicon hydride surface with a solution comprising hydrogen peroxide to convert said hydrophobic silicon hydride surface to a hydrophilic silicon hydroxide surface;
• exposing said hydrophilic silicon hydroxide surface to a metal halide to form a metal halide terminated silicon surface;
• and
• exposing said metal halide terminated silicon surface to water vapor to form a metal oxide dielectric film on said silicon surface.

A method of forming a CMOS integrated circuit comprising:

• forming a first sacrificial gate electrode over an n type semiconductor channel region;
• forming a second sacrificial gate electrode over a p type semiconductor channel region;
• forming a dielectric layer over said first and said second sacrificial gate electrode;
• planarizing said dielectric layer;
• revealing the top surface of said first and second sacrificial gate electrodes;
• removing said first sacrificial gate electrode to form a first opening over said n type channel region and removing said second sacrificial gate electrode to form a second opening over said p type semiconductor channel region;
• forming a gate dielectric layer in said first opening on said n type semiconductor channel region and in said second opening on said p type semiconductor channel region;
• forming a metal gate electrode material onto said gate dielectric layer in said first opening and onto said gate dielectric layer in second opening and above said planarized dielectric layer;
• and
• polishing said gate electrode material from above said interlayer dielectric to form a first gate electrode over said gate dielectric layer in said opening and a second gate electrode on said gate dielectric layer in said second opening.