Semiconductor device with multiple gate dielectric layers and method for fabricating the same

A semiconductor memory device, comprising:

• a silicon substrate comprising a cell region where NMOS transistors are formed and a peripheral region where NMOS and PMOS transistors are formed;
• a targeted silicon oxide layer on the silicon substrate in the cell region;
• an oxynitride layer on the silicon substrate in the peripheral region;
• a first gate structure formed on the targeted silicon layer and including an n+-type silicon electrode, a low resistance metal electrode, and a gate hard mask;
• a second gate structure formed on the oxynitride layer in an NMOS region of the peripheral region and including an n+-type silicon electrode, a low resistance metal electrode, and a gate hard mask;
• and
• a third gate structure formed on the oxynitride layer in a PMOS region of the peripheral region and including a p+-type silicon electrode, a low resistance metal electrode, and a gate hard mask.