Strained silicon, gate engineered Fermi-FETs

A field effect transistor comprising:

• a strained silicon channel in a substrate;
• source/drain regions in the substrate at opposite ends of the strained silicon channel;
• a gate insulating layer on the strained silicon channel, wherein doping of the strained silicon channel, doping of the substrate and/or a depth of the strained silicon channel are configured to produce nearly zero vertical electric field in the gate insulating layer and in the strained silicon channel adjacent thereto at a threshold voltage of the field effect transistor;
• and
• a gate on the gate insulating layer.

A field effect transistor comprising:

• a channel in a substrate;
• source/drain regions in the substrate at opposite ends of the channel;
• a gate insulating layer on the channel, wherein doping of the channel, doping of the substrate and/or a depth of the channel are configured to produce nearly zero vertical electric field in the gate insulating layer and in the channel adjacent thereto at a threshold voltage of the field effect transistor;
• and
• a gate on the gate insulating layer that is configured to provide a gate work function that is close to a mid-bandgap of silicon.

A field effect transistor comprising:

• a strained silicon channel in a substrate;
• source/drain regions in the substrate at opposite ends of the strained silicon channel;
• a gate insulating layer on the strained silicon channel;
• and
• a gate on the gate insulating layer that is configured to provide a gate work function that is close to a mid-bandgap of silicon.

A method of fabricating a field effect transistor comprising:

• epitaxially growing a relaxed silicon-germanium buffer layer on a silicon substrate;
• epitaxially growing a strained silicon channel on the relaxed silicon-germanium buffer layer;
• forming source/drain regions in the substrate at opposite ends of the strained silicon channel;
• forming a gate insulating layer on the strained silicon channel, wherein doping of the strained silicon channel, doping of the substrate and/or a depth of the strained silicon channel are configured to produce nearly zero vertical electric field in the gate insulating layer and in the strained silicon channel adjacent thereto at a threshold voltage of the field effect transistor;
• and
• forming a gate on the gate insulating layer that is configured to provide a gate work function that is close to a mid-bandgap of silicon.