Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell

A method for forming a non-volatile memory cell, the method comprising:

• forming a tunneling layer over a substrate surface;
• forming a charge trapping layer disposed on the first insulating layer;
• forming a blocking layer over the charge trapping layer;
• etching the blocking layer, the charge trapping layer, and the tunneling layer to expose a first portion of the substrate and to form a substantially vertical edge structure including edges of the blocking layer, the charge trapping layer, and the tunneling layer;
• forming a gate insulation layer on the first portion of the substrate surface to a thickness less than a thickness of the vertical edge structure;
• forming a gate layer disposed on the gate insulation layer and the blocking layer, the gate layer having a first edge and a second edge;
• and
• forming a source region and a drain region in the substrate substantially below the respective first and second edges of the gate layer.

A method for forming a non-volatile memory cell, the method comprising:

• forming a tunneling layer over a portion of a substrate surface, the substrate including a source region and a drain region;
• forming a charge trapping layer over either the source region or the drain region, the charge trapping layer having a length limited so as to allow any electrons stored in the trapping layer during a programming process to be erased during an erasing process;
• forming a blocking layer over the charge trapping layer;
• forming a gate insulation layer on a portion of the substrate surface not covered by the tunneling layer;
• and
• forming a gate layer disposed over the gate insulation layer and the blocking layer.

A method for forming a non-volatile memory cell, the method comprising:

• forming a tunneling layer over a first portion, a second portion, and third portion of a substrate;
• forming a charge trapping layer disposed on the tunneling layer;
• forming a blocking layer on the charge trapping layer;
• etching the blocking layer, the charge trapping layer, and the tunneling layer to expose the second portion of the substrate;
• forming a gate insulation layer on the second portion of the substrate;
• and
• forming a control gate disposed on the gate insulation layer and the blocking layers on the first and third portion of the substrate.

A method for forming a non-volatile memory cell, the method comprising:

• forming a tunneling layer over a first portion, a second portion, and a third portion of a substrate;
• forming a charge trapping layer disposed on the tunneling layer;
• forming a masking layer on the charge trapping layer;
• patterning the masking layer;
• using the patterned masking layer as a mask, etching the charge trapping layer and the tunneling layer to expose the second portion of the substrate;
• forming a blocking layer disposed on the charge trapping layer over the first and third portions of the substrate;
• forming an insulating layer on the second portion of the substrate;
• forming a control gate disposed on the insulating layer on the second portion of the substrate and on the blocking layer.