Method and apparatus for operating a non-volatile memory array
AssigneeMacronix International Co., Ltd.
InventorChih Yeh
Life of this patent
Estimating the term…
Abstract
A string of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of the selected memory cell. The charge storage state of the charge trapping structure affects the measured current.
Claims50
A method of operating an array of memory cells arranged in rows and columns, each of the columns including memory cells arranged in a series from a contact, each of the memory cells comprising a body region, a contact region, a bottom dielectric, a charge trapping structure having a charge storage state, a top dielectric, and a gate, the method comprising:
- applying a first bias arrangement to determine the charge storage state of the charge trapping structure of at least a selected memory cell in the series, wherein the first bias arrangement electrically couples the contact region of the selected memory cell to the contact by causing inversion in the body region of memory cells between the selected memory cell and the contact;
- and
- measuring current flowing between the body region of the selected memory cell and the contact to determine the charge storage state of the charge trapping structure of the selected memory cell.
A nonvolatile memory, comprising:
- a plurality of bit lines;
- a memory array including a plurality of memory cells arranged in rows and columns, each of the columns including memory cells arranged in a series from a contact, each of the columns coupled to a corresponding bit line of the plurality of bit lines at the contact, each memory cell including:
- a body region;
- a contact region coupled to the body region;
- a bottom dielectric coupled to the body region;
- a charge trapping structure coupled to the bottom dielectric having a charge storage state;
- and
- a top dielectric coupled to the charge trapping structure;
- a plurality of word lines coupled to the top dielectrics of the plurality of memory cells, each word line of the plurality of word lines providing voltage as a gate for memory cells coupled to said each word line;
- and
- logic coupled to the plurality of bit lines and the plurality of word lines, the logic applying a first bias arrangement to determine the charge storage state of the charge trapping structure of at least a selected memory cell, and the logic measuring current flowing in response to the first biasing arrangement to determine the charge storage state of the charge trapping structure of the selected memory cell, the current flowing between the body region of the selected memory cell and the contact region of the selected memory cell.
A method of manufacturing nonvolatile memory, comprising:
- providing a semiconductor substrate;
- providing a plurality of bit lines;
- providing a memory array including a plurality of memory cells arranged in rows and columns, each of the columns including memory cells arranged in a series from a contact, each of the columns coupled to a corresponding bit line of the plurality or bit lines at least at the contact, each memory cell including:
- a body region;
- a contact region coupled to the body region;
- a bottom dielectric coupled to the body region;
- a charge trapping structure coupled to the bottom dielectric having a charge storage state;
- and
- a top dielectric coupled to the charge trapping structure;
- providing a plurality of word lines coupled to the, top dielectrics of the plurality of memory cells, each word line of the plurality of word lines providing voltage as a gate for memory cells coupled to said each word line;
- and
- providing logic coupled to the plurality of bit lines and the plurality of word lines, the logic applying a first bias arrangement to determine the charge storage state of the charge trapping structure of at least a selected memory cell, and the logic measuring current flowing in response to the first biasing arrangement to determine the charge storage state of the charge trapping structure of the selected memory cell, the current flowing between the body region of the selected memory cell and the contact region of the selected memory cell.
Dependencies are inferred from the claim text.