Charge trap insulator memory device
AssigneeHynix Semiconductor Inc.
InventorsHee Kang, Jin Ahn, Jae Lee
Life of this patent
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Abstract
A charge trap insulator memory device comprises a bottom word line, a P-type float channel formed at the bottom word line and kept at a floating state, a charge trap insulator formed on the P-type float channel, a top word line formed on the charge trap insulator in parallel with the bottom word line, and a N-type drain region and a N-type source region formed at both sides of the float channel. As a result, in the float gate memory device, a retention characteristic is improved, and cell integrated capacity is also increased due to a plurality of float gate cell arrays deposited vertically using a plurality of cell oxide layers.
Claims17
A charge trap insulator memory device comprising:
- a bottom word line;
- a float channel layer formed on the bottom word line and kept at a floating state;
- a charge trap insulator, formed on the float channel layer, where data are stored;
- and
- a top word line formed on the charge trap insulator in parallel with the bottom word line,
- wherein data are written in the charge trap insulator depending on levels of the bottom word line and the top word line, and
- data are read according to different channel resistance induced to the float channel depending on polarity states of charges stored in the charge trap insulator.
A charge trap insulator memory device comprising:
- a bottom word line;
- a first insulating layer formed on the bottom word line;
- a P-type float channel formed on the first insulating layer and kept at a floating state;
- a second insulating layer formed on the P-type float channel;
- a charge trap insulator, formed on the second insulating layer, where charges are stored;
- a third insulating layer formed on the charge trap insulator;
- a top word line formed on the third insulating layer;
- and
- a N-type drain region and a N-type source region formed at both sides of the float channel,
- wherein data are written in the charge trap insulator depending on a level of the top word line while the bottom word line is selected, and
- data are read according to different channel resistance induced to the float channel depending on polarity states of charges stored in the charge trap insulator.
A charge trap insulator memory device comprising:
- a plurality of unit memory cell arrays each including a plurality of charge trap insulator memory cells and deposited as a multiple layer,
- wherein the charge trap insulator memory cell comprises:
- a bottom word line;
- a first insulating layer formed on the bottom word line;
- a P-type float channel formed on the first insulating layer and kept at a floating state;
- a second insulating layer formed on the P-type float channel;
- a charge trap insulator, formed on the second insulating layer, where charges are stored;
- a third insulating layer formed on the charge trap insulator;
- a top word line formed on the third insulating layer;
- and
- a N-type drain region and a N-type source region formed at both sides of the float channel,
- wherein data are written in the charge trap insulator depending on a level of the top word line while the bottom word line is selected, and
- data are read according to different channel resistance induced to the float channel depending on polarity states of charges stored in the charge trap insulator.
A charge trap insulator memory device comprising:
- a plurality of unit memory cell arrays each including a plurality of charge trap insulator memory cells and deposited as a multiple layer,
- wherein the charge trap insulator memory cell comprises:
- a bottom word line;
- a first insulating layer formed on the bottom word line;
- a P-type float channel formed on the first insulating layer and kept at a floating state;
- a second insulating layer formed on the P-type float channel;
- a charge trap insulator, formed on the second insulating layer, where charges are stored;
- a third insulating layer formed on the charge trap insulator;
- a top word line formed on the third insulating layer;
- and
- a N-type drain region and a N-type source region formed at both sides of the float channel,
- wherein the plurality of memory cells in each of the plurality of unit memory cell arrays are connected in common to the bottom word line,
- data are written in the charge trap insulator depending on a level of the top word line while the bottom word line is selected, and
- data are read according to different channel resistance induced to the float channel depending on polarity states of charges stored in the charge trap insulator.
Dependencies are inferred from the claim text.