US 2006/0138519 A1 · Float gate memory device

Abstract

A float gate memory device comprises a bottom word line, a float channel layer formed on the bottom word line and kept at a floating state, a float gate, and a top word line formed on the float gate in parallel with the bottom word line. In the float gate formed on the float channel, data are stored. Here, data are written in the float gate depending on levels of the bottom word line and the top word line, and different channel resistances are induced to the float channel depending on polarity states of charges stored in the float gate, so that data are read. As a result, in the float gate memory device, a retention characteristic is improved, and cell integrated capacity is also increased due to a plurality of float gate cell arrays deposited vertically using a plurality of cell oxide layers.

Claims31

Dependent claims

A float gate memory device comprising:

a bottom word line;
a float channel layer formed on the bottom word line and kept at a floating state;
a float gate, formed on the float channel, where data are stored;
and
a top word line formed on the float gate in parallel with the bottom word line,
wherein data are written in the float gate depending on levels of the bottom word line and the top word line, and
data are read according to different channel resistances induced to the float channel depending on polarity states of charges stored in the float gate.

4 more elements

A float gate memory device comprising:

a plurality of serially connected memory cells where data applied through a bit line are stored in a float gate depending on potentials applied to a top word line and a bottom word line or data stored in the float gate are outputted to the bit line;
a first switching element for selectively connecting the plurality of memory cells to a bit line in response to a first selecting signal;
and
a second switching element for selectively connecting the plurality of memory cells to a sensing line in response to a second selecting signal,
wherein each of the plurality of memory cells comprises:
a first insulating layer formed on the bottom word line;
a P-type float channel, formed on the first insulating layer, whose resistance is changed depending on the polarity of the float gate;
a N-type drain region and a N-type source region formed at both sides of the P-type float channel;
a second insulating layer formed on the P-type float channel;
the float gate formed on the second insulating layer;
and
a third insulating layer formed on the float gate and under the top word line.

9 more elements

A float gate memory device comprising:

a plurality of top word lines arranged in parallel with a plurality of bottom word lines in a row direction;
a plurality of bit lines arranged in a column direction;
a plurality of sensing lines arranged perpendicular to the plurality of bit lines;
a plurality of memory cell arrays arranged where the plurality of top word lines, the plurality of bottom word lines and the plurality of bit lines are crossed;
and
a plurality of sense amplifiers, corresponding one by one to the plurality of bit lines, for sensing and amplifying data in the bit line,
wherein each of the plurality of memory cell arrays comprises:
a plurality of serially connected memory cells where data applied through a bit line are stored in a float gate depending on potentials applied to a top word line and a bottom word line or data stored in the float gate are outputted to the bit line;
a first switching element for selectively connecting the plurality of memory cells to a bit line in response to a first selecting signal;
and
a second switching element for selectively connecting the plurality of memory cells to a sensing line in response to a second selecting signal,
wherein each of the plurality of memory cells comprises:
a first insulating layer formed on the bottom word line;
a P-type float channel, formed on the first insulating layer, whose resistance is changed depending on the polarity of the float gate;
a N-type drain region and a N-type source region formed at both sides of the P-type float channel;
a second insulating layer formed on the P-type float channel;
the float gate formed on the second insulating layer;
and
a third insulating layer formed on the float gate and under the top word line.

16 more elements

Dependencies are inferred from the claim text.

Float gate memory device

Life of this patent

Float gate memory device

Life of this patent

Abstract

Claims31