Semiconductor device with silicon-germanium gate electrode and method for manufacturing thereof

A method for manufacturing a semiconductor device, comprising:

• forming a high-k dielectric film as a gate dielectric film on a substrate;
• forming a seed Si film on the high-k dielectric film;
• forming a SiGe film on the seed Si film;
• and
• patterning the SiGe film and the seed Si film to form a gate electrode, and patterning the high-k dielectric film;
• and
• forming doped regions in an upper region of the substrate by ion implantation, using the gate electrode as a mask.

A method for manufacturing a semiconductor device, comprising:

• forming a laminated gate dielectric film including an underlying interfacial layer and a high-k dielectric film, having a higher dielectric constant than the underlying interfacial layer, on a substrate;
• forming a seed Si film with a thickness of at least 0.1 nm and smaller than 5 nm on the high-k dielectric film;
• forming a SiGe film at a temperature of at least 450° C. and less than 500° C. on the seed Si film
• forming a lower cap Si film at the same temperature as forming of the SiGe film, with a thickness of 0.5 at least nm and no more than 5 nm, on the SiGe film;
• forming an upper cap Si film on the lower cap Si film at a temperature higher than the temperature of forming the lower SiGe film;
• patterning the upper cap Si film, the lower cap Si film, the SiGe film, and the seed Si film to form a gate electrode, and patterning the high-k dielectric film and the underlying interfacial layer;
• forming extension regions in an upper region of the substrate by ion implantation, using the gate electrode as a mask and performing a thermal process;
• forming sidewalls covering sides of the gate electrode;
• forming source-drain regions in an upper region of the substrate by ion implantation, using the sidewalls and gate electrode as a mask, and performing a thermal process;
• and
• forming silicide layers in upper portions of the upper cap Si film and the source-drain regions by saliciding.

A method for manufacturing a semiconductor device including n-type circuit regions and p-type circuit regions, the method comprising:

• forming p-type well regions in an upper region of a substrate of the n-type circuit regions, and forming n-type well regions in an upper region of the substrate of the p-type circuit regions;
• forming a laminated gate dielectric film, including an underlying interfacial layer and a high-k dielectric film, having a higher dielectric constant than the underlying interfacial layer, on the p-type well regions and the n-type well regions;
• forming a seed Si film with a thickness of at least 0.1 nm and smaller than 5 nm on the high-k dielectric film;
• forming a SiGe film at a temperature of at least 450° C. and less than 500° C. on the seed Si film
• forming a lower cap Si film at the same temperature as forming of the SiGe film, with a thickness of at least 0.5 nm and no more than 5 nm, on the SiGe film;
• forming an upper cap Si film on the lower cap Si film at a temperature higher than the temperature of forming the lower SiGe film;
• patterning the upper cap Si film, the lower cap Si film, the SiGe film, and the seed Si film to form a gate electrode, and patterning the high-k dielectric film and the underlying interfacial layer;
• forming n-type extension regions in an upper region of the p-type well regions by ion implantation of n-type impurities using the gate electrode as a mask and performing a thermal process;
• forming p-type extension regions in upper layer of the p-type well regions by ion implantation of p-type impurities using the gate electrode as a mask and performing a thermal process;
• forming sidewalls covering sides of the gate electrode;
• forming n-type source-drain regions in an upper region of the p-type well regions through ion implantation of n-type impurities using the sidewalls and gate electrode as a mask and performing a thermal process;
• forming p-type source-drain regions in an upper region of the p-type well regions by ion implantation of p-type impurities using the sidewalls and gate electrode as a mask and performing a thermal process;
• and
• forming silicide layers in upper portions of the upper cap Si film and the source-drain regions by saliciding.