Tensile strained substrate

A metal oxide semiconductor field effect transistor (MOSFET), comprising:

• a gate insulator above a layer above the substrate;
• a substrate having a gate formed above the substrate;
• a gate above the gate insulator;
• a spacer for the gate and gate;
• an etch stop layer above the spacer, the gate, and the layer;
• a dielectric layer above the etch stop layer;
• and
• wherein at least one of the etch stop layer, and the dielectric layer comprises a high compression deposition material, whereby the layer increases in tensile stain due to the high compression deposition material.

An integrated circuit device, comprising:

• a substrate comprising a layer of silicon germanium having a layer of silicon material formed thereon, and at least one of a gate insulating layer formed on the silicon layer, and a gate conductive layer formed on the gate insulating layer;
• an etch stop layer above the gate;
• and
• an interlevel dielectric layer above the etch stop layer, wherein the etch stop layer or the interlevel dielectric layer is formed in a highly compressive deposition process that compresses the layer of silicon material, causing increased tensile strain therein.