Layout of semiconductor memory device and method of controlling capacitance of dummy cell
AssigneeSamsung Electronics Co., Ltd.
InventorJin Choi
Life of this patent
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Abstract
Provided are a layout of a semiconductor memory device capable of minimizing an occupation area of a dummy cell array and a method of controlling capacitance of a dummy cell to be same with that of the memory cell. The layout includes a dummy cell connected to one side of a sense amplifier, in which the dummy cell has a capacitance identical to a capacitance of the memory cell. The dummy cell is connected to one side of a sense amplifier connected to the memory cell and arranged in a column direction of the semiconductor substrate.
Claims21
A layout of a semiconductor memory device, comprising:
- a semiconductor substrate;
- a plurality of memory cells storing data, the plurality of memory cells being arranged in row and column directions on the semiconductor substrate;
- a sense amplifier connected to each row of memory cells to comprise a plurality of sense amplifiers, the sense amplifiers being arranged in the column direction of the semiconductor substrate;
- a bit line connected to each sense amplifier, the bit line being extended in the row direction;
- and
- for each sense amplifier, a dummy cell connected to the sense amplifier, the dummy cell having a capacitance identical to a capacitance of the row of memory cells associated with the same sense amplifier.
A layout of a semiconductor memory device, comprising:
- a semiconductor substrate;
- a plurality of memory cells storing data, the plurality of memory cells being arranged in row and column directions on the semiconductor substrate;
- a sense amplifier connected to each row of memory cells to comprise a plurality of sense amplifiers, the sense amplifiers being arranged in the column direction of the semiconductor substrate;
- a bit line connected to one side of each sense amplifier, the bit line being extended in the row direction;
- and
- for each sense amplifier, a dummy cell having a capacitance identical to a capacitance of the row of memory cells associated with the same sense amplifier, wherein the sense amplifier is disposed between the dummy cell and the memory cell.
A layout of a semiconductor memory device, comprising:
- a semiconductor substrate;
- a plurality of memory cells storing data, the plurality of memory cells being arranged in row and column directions on the semiconductor substrate;
- a sense amplifier connected to each row of memory cells to comprise a plurality of sense amplifiers, the sense amplifiers being arranged in the column direction of the semiconductor substrate;
- a bit line connected to one side of each sense amplifier, the bit line being extended in the row direction;
- and
- for each sense amplifier, a dummy cell disposed between the sense amplifier and the row of memory cells connected to the sense amplifier, the dummy cell having a capacitance identical to a capacitance of the row of memory cells associated with the same sense amplifier.
A method of controlling capacitance of a dummy cell, the method comprising:
- setting capacitance of each memory cell storing data, the each memory cell being arranged in row and column directions;
- and
- forming a dummy cell having a capacitance identical to a capacitance of the memory cell, the dummy cell being connected to one side of a sense amplifier connected to the memory cell and being arranged in the column direction of a semiconductor substrate.
Dependencies are inferred from the claim text.