Semiconductor integrated circuit devices including SRAM cells and flash memory cells and methods of fabricating the same

A semiconductor integrated circuit device comprising:

• an integrated circuit substrate having an SRAM cell region, a flash memory cell region, and a logic circuit region;
• an isolation layer provided in a predetermined region of the substrate to define an access/driver transistor active region and a load transistor active region in the SRAM cell region, a flash memory cell active region in the flash memory cell region, and first to fourth logic transistor active regions in the logic circuit region;
• an access gate pattern crossing over first and second portions of the access/driver transistor active region, the access gate pattern having a main access gate electrode and a dummy access gate electrode which are sequentially stacked;
• a first common gate pattern crossing over the access/driver transistor active region between the first and second portions as well as the load transistor active region, the first common gate pattern having a first main common gate electrode and a first dummy common gate electrode which are sequentially stacked;
• a second common gate pattern crossing over the access/driver transistor active region between the first common gate pattern and the second portion as well as the load transistor active region, the second common gate pattern having a second main common gate electrode and a second dummy common gate electrode which are sequentially stacked;
• a flash memory cell gate pattern including a control gate electrode crossing over the flash memory cell active region and a floating gate interposed between the control gate electrode and the flash memory cell active region;
• a first NMOS gate pattern crossing over the first logic transistor active region, the first NMOS gate pattern having a first main NMOS gate electrode and a first dummy NMOS gate electrode which are sequentially stacked;
• a first PMOS gate pattern crossing over the second logic transistor active region, the first PMOS gate pattern having a first main PMOS gate electrode and a first dummy PMOS gate electrode which are sequentially stacked;
• a second NMOS gate pattern crossing over the third logic transistor active region, the second NMOS gate pattern having a second main NMOS gate electrode and a second dummy NMOS gate electrode which are sequentially stacked;
• and
• a second PMOS gate pattern crossing over the fourth logic transistor active region, the second PMOS gate pattern having a second main PMOS gate electrode and a second dummy PMOS gate electrode which are sequentially stacked.

A method of fabricating a semiconductor integrated circuit device, comprising:

• providing an integrated circuit substrate having an SRAM cell region, a flash memory cell region, and a logic circuit region;
• forming an isolation layer in a predetermined region of the substrate to define an SRAM cell active region, a flash memory cell active region and a logic transistor active region, in the SRAM cell region, the flash memory cell region and the logic circuit region, respectively;
• and
• forming an SRAM cell gate pattern, a flash memory cell gate pattern and a logic gate pattern crossing over the SRAM cell active region, the flash memory cell active region and the logic transistor active region, respectively,
• wherein the SRAM cell gate pattern is formed to have a main SRAM cell gate electrode and a dummy SRAM cell gate electrode which are sequentially stacked, the flash memory cell gate pattern is formed to have a control gate electrode crossing over the flash memory cell active region as well as a floating gate interposed between the control gate electrode and the flash memory cell active region, and the logic gate pattern is formed to have a main logic gate electrode and a dummy logic gate electrode which are sequentially stacked.

A method of fabricating a semiconductor integrated circuit device, comprising:

• providing an integrated circuit substrate having an SRAM cell region, a flash memory cell region and a logic circuit region;
• forming an isolation layer in a predetermined region of the substrate to define an access/driver transistor active region and an load transistor active region in the SRAM cell region, a flash memory cell active region in the flash memory cell region, and first to fourth logic transistor active regions in the logic circuit region;
• and
• forming an access gate pattern crossing over first and second portions of the access/driver transistor active region, a first common gate pattern crossing over the access/driver transistor active region between the first and second portions as well as the load transistor active region, a second common gate pattern crossing over the access/driver transistor active region between the first common gate pattern and the second portion as well as the load transistor active region, a flash memory cell gate pattern including a control gate electrode crossing over the flash memory cell active region as well as a floating gate interposed between the control gate electrode and the flash memory cell active region, a first NMOS gate pattern crossing over the first logic transistor active region, a first PMOS gate pattern crossing over the second logic transistor active region, a second NMOS gate pattern crossing over the third logic transistor active region and a second PMOS gate pattern crossing over the fourth logic transistor active region,
• wherein the access gate pattern is formed to have a main access gate electrode and a dummy access gate electrode which are sequentially stacked,
• wherein the first common gate pattern is formed to have a first main common gate electrode and a first dummy common gate electrode which are sequentially stacked,
• wherein the second common gate pattern is formed to have a second main common gate electrode and a second dummy common gate electrode which are sequentially stacked,
• wherein the first NMOS gate pattern is formed to have a first main NMOS gate electrode and a first dummy NMOS gate electrode which are sequentially stacked,
• wherein the first PMOS gate pattern is formed to have a first main PMOS gate electrode and a first dummy PMOS gate electrode which are sequentially stacked,
• wherein the second NMOS gate pattern is formed to have a second main NMOS gate electrode and a second dummy NMOS gate electrode which are sequentially stacked, and
• wherein the second PMOS gate pattern is formed to have a second main PMOS gate electrode and a second dummy PMOS gate electrode which are sequentially stacked.