Methods of forming semiconductor constructions
AssigneeMicron Technology, Inc.
InventorArup Bhattacharyya
Life of this patent
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Abstract
Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed crystalline lattice. The relaxed crystalline lattice can comprise appropriately-doped silicon/germanium. The strained crystalline lattice can comprise, for example, appropriately doped silicon, or appropriately-doped silicon/germanium. The CMOS inverter can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic).
Claims11
1-61. (canceled)
A method of forming a semiconductor construction, comprising:
- providing a first semiconductor material, the first semiconductor material having at least one p-type doped region therein;
- forming a transistor gate over the first semiconductor material;
- forming n-type doped source/drain regions extending downwardly into the first semiconductor material from adjacent the gate;
- forming a second semiconductive semiconductor material over the gate;
- the second semiconductor material having at least one n-type doped region and having p-type doped source/drain regions therein;
- the p-type doped source/drain regions extending upwardly from adjacent the gate and into the second semiconductor material, the p-type doped source/drain regions not extending entirely through the second semiconductor material;
- the n-type doped source/drain regions and transistor gate together forming an NFET device, and the p-type doped source/drain regions and transistor gate together forming a PFET device stacked over the NFET device;
- and
- forming an n-type doped third semiconductor material extending from one of the n-type source/drain regions to an n-type doped region of the second semiconductive material.
A method of forming a semiconductor construction, comprising:
- providing a substrate;
- forming a first layer over the substrate;
- the first layer comprising p-type doped Si/Ge and having a relaxed crystalline lattice;
- forming a second layer over the first layer;
- the second layer comprising p-type doped Si/Ge and having a strained crystalline lattice;
- forming a transistor gate over the second layer;
- forming n-type doped source/drain regions extending downwardly from adjacent the gate and into the first and second layers;
- the n-type doped source/drain regions and transistor gate together forming an NFET device;
- forming a third layer over the transistor gate;
- the third layer comprising n-type doped Si/Ge;
- forming a fourth layer over the third layer;
- the fourth layer comprising n-type doped silicon;
- forming p-type doped source/drain regions extending upwardly from adjacent the gate and into the third layer;
- the p-type doped source/drain regions and transistor gate together forming a PFET device;
- and
- forming an electrical interconnect which electrically connects the third layer to one of the NFET device source/drain regions.
Dependencies are inferred from the claim text.