Method for the generation of static noise check data
AssigneeFujitsu Limited
InventorYoichiro Ishikawa
Life of this patent
Estimating the term…
Abstract
In the static noise check of the LSI hierarchical design, in order to reduce the data volume of the common parts and load of the design operation and DA, when a plurality of cores, comprising the same sub-chips, are present, the static noise check data for the whole chip is generated from the core-level design data of one of the cores, and the chip-level design data.
Claims18
A genaration method of static noise check data in a hierarchical design comprising a plurality of hierarchies, such as chip level, core level and sub-chip level etc. for an LSI comprizing a plurality of cores consisting of the same sub-chips:
- having core-level design data only in a single core among a plurality of the cores comprising the same sub-chips;
- and generating static noise check data of the cores, which do not have the core-level design data, from the core-level design data of the single core and chip-level design data of each core which does not have the core-level design data.
A genaration method of static noise check data in a hierarchical design comprising a plurality of hierarchies, such as chip level, core level and sub-chip level etc. for an LSI comprising a plurality of cores consisting of the same sub-chips:
- having core-level design data only in a single core among a plurality of the cores comprising the same sub-chips;
- generating static noise check data of the cores, which do not have the core-level design data, from the core-level design data of the single core and chip-level design data of each core which does not have the core-level design data;
- clipping a chip-level wiring data on the chip at the outer frame of each core or sub-chips;
- storing the chip-level wiring data as chip wiring data on each core;
- and
- adding the data to the static noise check data of each core and sub-chip.
A genaration method of static noise check data in a hierarchical design comprising a plurality of hierarchies, such as chip level, core level and sub-chip level etc. for an LSI comprizing a plurality of cores consisting of the same sub-chips:
- having core-level design data only in a single core among a plurality of the cores consisting of the same sub-chips;
- and generating the whole chip static noise check data from core-level design data of the single core and chip-level design data.
A generation device of static noise check data in a hierarchical design comprising a plurality of hierarchies, such as chip level, core level and sub-chip level etc. for an LSI comprizing a plurality of cores consisting of the same sub-chips, comprising:
- a chip database storing a chip-level placement/wiring data;
- a core/sub-chip database, in which core/sub-chip level placement/wiring data is stored, only storing a placement/wiring data of a single core when there are a plurality of cores comprising same sub-chips;
- a chip data extraction unit, which retrieves the placement data on the chip from the chip database and stores the data in first memory means;
- a check data extraction unit, which retrieves the core/sub-chip initial static noise check data from the core/sub-chip database and stores the data in second memory means;
- an on-chip placement data conversion unit, which converts the core/sub-chip initial static noise check data stored in the second memory means into a core/sub-chip processed static noise check data based on the on-chip placement data stored in the first memory means and stores the converted data in third memory means;
- a chip wiring clipping unit, which retrieves the on-chip wiring data from the chip database and stores the data in fourth memory means;
- and
- an on-chip wiring data addition unit, which clips the on-chip wiring data with reference to the core/sub-chip processed static noise check data stored in the third memory means and the on-chip wiring data stored in the fourth memory means and generates the core/sub-chip final static noise check data from the clipped data by adding the sub-chip processed static noise check data.
A generation device of static noise check data in a hierarchical design comprising a plurality of hierarchies, such as chip level, core level and sub-chip level etc. for an LSI comprizing a plurality of cores consisting of the same sub-chips, comprising:
- a chip database storing a chip-level placement/wiring data;
- a core/sub-chip database, in which core/sub-chip level placement/wiring data is stored, only storing a placement/wiring data of a single core when there are a plurality of cores comprising same sub-chips;
- a chip data extraction unit, which retrieves the placement data on the chip from the chip database and stores the data in first memory means;
- a first check data extraction unit, which retrieves the core/sub-chip initial static noise check data from the core/sub-chip database and stores the data in second memory means;
- an on-chip placement data converion unit, which converts the core/sub-chip initial static noise check data stored in the second memory means into a core/sub-chip processed static noise check data based on the on-chip placement data stored in the first memory means and stores the converted data in third memory means;
- a second check data extraction unit, which retrieves the chip initial static noise check data from the chip database and stores the data in fourth memory means;
- and
- an on-chip wiring data addition unit, which generates the core/sub-chip final static noise check data by adding the sub-chip processed static noise check data stored in the third memory means to the core/sub-chip initial static noise check data stored in the fourth memory means.
A generation method of static noise check data, using a generation device of static noise check data in a hierarchical design comprising a plurality of hierarchies, such as chip level, core level and sub-chip level etc. for an LSI comprizing a plurality of cores consisting of the same sub-chips, and the generation device involves a chip database storing a chip-level placement/wiring data and a core/sub-chip database, in which core/sub-chip level placement/wiring data is stored, only storing a placement/wiring data of a single core when there are a plurality of cores comprising the same sub-chips, comprising:
- a chip data extraction step, which retrieves the placement data on the chip from the chip database and stores the data in a first memory means;
- a check data extraction step, which retrieves the core/sub-chip initial static noise check data from the core/sub-chip database and stores the data in a second memory means;
- an on-chip placement data conversion step, which converts the core/sub-chip initial static noise check data stored in the second memory means into a core/sub-chip processed static noise check data based on the on-chip placement data stored in the first memory means and store the converted data in a third memory means;
- a chip wiring clipping step, which retrieves the on-chip wiring data from the chip database and stores the data in a fourth memory means;
- and
- an on-chip wiring data addition step, which clips the on-chip wiring data with reference to the core/sub-chip processed static noise check data stored in the third memory means and the on-chip wiring data stored in the fourth memory means and generates the core/sub-chip final static noise check data from the clipped data by adding the sub-chip processed static noise check data.
A generation method of static noise check data, using a generation device of static noise check data in a hierarchical design comprising a plurality of hierarchies, such as chip level, core level and sub-chip level etc. for an LSI comprizing a plurality of cores consisting of the same sub-chips, and the generation device involves a chip database storing a chip-level placement/wiring data and a core/sub-chip database, in which core/sub-chip level placement/wiring data is stored, only storing a placement/wiring data of a single core when there are a plurality of cores comprising the same sub-chips, comprising:
- a chip data extraction step, which retrieves the placement data on the chip from the chip database and stores the data in a first memory means;
- a first check data extraction step, which retrieves the core/sub-chip initial static noise check data from the core/sub-chip database and stores the data in a second memory means;
- an on-chip placement data conversion step, which converts the core/sub-chip initial static noise check data stored in the second memory means into a core/sub-chip processed static noise check data based on the on-chip placement data stored in the first memory means and stores the converted data in third memory means;
- a second check data extraction step, which retrieves the chip initial static noise check data from the chip database and stores the data in a fourth memory means;
- and
- a core/sub-chip wiring data addition step, which generates the chip final static noise check data by adding the core/sub-chip processed static noise check data stored in the third memory means to the chip initial static noise check data stored in the fourth memory means.
A computer readable medium storing a generation program of static noise check data, which makes a computer operate as a generation device of static noise check data in a hierarchical design comprising a plurality of hierarchies, such as chip level, core level and sub-chip level etc. for an LSI comprizing a plurality of cores consisting of the same sub-chips, and the generation device involves a chip database storing a chip-level placement/wiring data and a core/sub-chip database, in which core/sub-chip level placement/wiring data is stored, only storing a placement/wiring data of a single core when there are a plurality of cores comprising the same sub-chips, comprising:
- a chip data extraction step, which retrieves the placement data on the chip from the chip database and stores the data in a first memory means;
- a check data extraction step, which retrieves the core/sub-chip initial static noise check data from the core/sub-chip database and stores the data in a second memory means;
- an on-chip placement data conversion step, which converts the core/sub-chip initial static noise check data stored in the second memory means into a core/sub-chip processed static noise check data based on the on-chip placement data stored in the first memory means and stores the converted data in a third memory means;
- a chip wiring clipping step, which retrieves the on-chip wiring data from the chip database and stores the data in a fourth memory means;
- and
- an on-chip wiring data addition step, which clips the on-chip wiring data with reference to the core/sub-chip processed static noise check data stored in the third memory means and the on-chip wiring data stored in the fourth memory means and generates the core/sub-chip final static noise check data from the clipped data by adding the sub-chip processed static noise check data.
A computer readable medium storing a generation program of static noise check data, which makes a computer operate as a generation device of static noise check data in a hierarchical design comprising a plurality of hierarchies, such as chip level, core level and sub-chip level etc. for an LSI comprizing a plurality of cores consisting of the same sub-chips, and the generation device involves a chip database storing a chip-level placement/wiring data and a core/sub-chip database, in which core/sub-chip level placement/wiring data is stored, only storing a placement/wiring data of a single core when there are a plurality of cores comprising the same sub-chips, comprising:
- a chip data production step, which retrieves the placement data on the chip from the chip database and stores the data in a first memory means;
- a first check data extraction step, which retrieves the core/sub-chip initial static noise check data from the core/sub-chip database and stores the data in a second memory means;
- an on-chip placement data conversion step, which converts the core/sub-chip initial static noise check data stored in the second memory means into a core/sub-chip processed static noise check data based on the on-chip placement data stored in the first memory means and stores the converted data in a third memory means;
- a second check data extraction step, which retrieves the chip initial static noise check data from the chip database and stores the data in a fourth memory means;
- and
- an core/sub-chip wiring data addition step, which generates the chip final static noise check data by adding the core/sub-chip processed static noise check data stored in the third memory means to the chip initial static noise check data stored in the fourth memory means.
Dependencies are inferred from the claim text.