Selectively reducing the number of cell evaluations in a hardware simulation
AssigneeMentor Graphics Corporation
InventorsSteven Greenberg, Du Nguyen, Joseph Rodriguez
Life of this patent
Estimating the term…
Abstract
An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time.
Claims48
A method of simulating an electrical circuit comprising a plurality of cells to produce simulation results, the method comprising:
- performing an initial evaluation of at least a sub-plurality of the plurality of cells to determine whether each of the at least a sub-plurality of the plurality of cells is active or inactive;
- sorting the active cells determined as a result of the initial evaluation into at least one first active cell group;
- sorting the inactive cells determined as a result of the initial evaluation into at least one second inactive cell group;
- repetitively re-evaluating said at least a sub-plurality of the plurality of cells to determine whether an activity status of each of the at least a sub-plurality of the plurality of cells has changed from active to inactive or from inactive to active;
- sorting cells that have changed from inactive cells to active cells into said at least one first active cell group and sorting cells that have changed from active cells to inactive cells into said at least one second inactive cells group;
- and
- processing at least some of the simulation results from the cells of the at least one first active cell group differently from the processing of at least some of the simulation results from the cells of the at least one second inactive cell group.
A system for simulating an integrated circuit, comprising:
- a first plurality of active cells;
- and
- a second plurality of inactive cells, wherein at least one of the first plurality of active cells and at least one of the second plurality of inactive cells is coupled with a first common potential clock and at least another one of the first plurality of active cells and at least another one of the second plurality of inactive cells is coupled with a second common potential clock, the first common potential clock being delayed by a first common time delay and the second common potential clock being delayed by a second common time delay, and wherein the first common time delay is different from the second common time delay.
In a method for simulating an electrical circuit comprising a plurality of cells, a method for determining a potential clock signal from a plurality of candidate potential clock signals that are each coupled to a respective input to each of the plurality of cells, the method comprising:
- monitoring the plurality of candidate potential clock signals during a simulation time period;
- counting changes in a value of the candidate potential clock signals during said simulation time period;
- designating a candidate potential clock signal that has a greatest number of value changes during said simulation time period as the potential clock input for said plurality of cells.
In a simulation method for simulating an electrical circuit comprising a plurality of cells, classifying at least a plurality of said cells as inactive or active in accordance with the following method:
- monitoring an output, an internal state, a potential clock input, and at least one other input for each of the plurality of cells;
- and
- classifying a cell as inactive if the monitored output and internal state for the cell do not change for at least two transitions of the potential clock input.
A method of simulating an electrical circuit comprising cells, the method comprising:
- designating at least one input to a plurality of cells as a potential clock signal;
- assigning an activity classification to at least one of the plurality of cells, wherein the at least one of a plurality of cells receives the potential clock signal as an input, wherein the assigned activity classification is an inactive status in the event the at least one of a plurality of cells is inactive, and wherein the assigned activity classification is an active status in the event the at least one of a plurality of cells is active;
- during simulation of the integrated circuit, bypassing processing of at least some simulation results from said at least one of a plurality of cells that are produced when the assigned activity classification for said at least one of the plurality of cells is inactive.
The method of claim 26 wherein the act of analyzing activity of the at least one of the plurality of cells comprises monitoring outputs from the at least one of a plurality of cells to determine changes in said monitored outputs.
A method of simulating an electrical circuit comprising cells, the method comprising:
- storing at least one array, wherein the at least one array comprises:
- at least one first sub-array comprising a first plurality of entries corresponding to a first plurality of active cells within the electrical current being simulated;
- at least one second sub-array comprising a second plurality of entries corresponding to a second plurality of inactive cells within the electrical current being simulated;
- and
- manipulating at least one of the sub-arrays based upon a change in status of at least one simulated cell from active to inactive or from inactive to active.
A system for simulating hardware, comprising:
- a model of a hardware configuration, wherein the hardware configuration comprises a plurality of cells;
- and
- a hardware simulator comprising at least one array, the at least one array comprising:
- at least one first sub-array comprising a plurality of pointers to a first sub-plurality of the plurality of cells, the first sub-plurality comprising active cells;
- and
- at least one second sub-array comprising a plurality of pointers to a second sub-plurality of the plurality of cells, the second sub-plurality comprising inactive cells.
A method of hardware simulation, comprising:
- identifying at least two delay elements each positioned between one of a plurality of cells of a hardware configuration and an input signal;
- determining whether the at least two delay elements represent a substantially similar delay;
- and
- in response to a determination that the at least two delay elements do represent the substantially similar delay, merging the at least two delay elements into a single delay element for simulation.
An apparatus for simulating an electrical circuit comprising plural cells, the apparatus comprising:
- means for storing an array, wherein the array comprises:
- a first sub-array comprising a first plurality of entries corresponding to a first plurality of active cells within the electrical circuit to be simulated;
- a second sub-array comprising a second plurality of entries corresponding to a second plurality of inactive cells within the electrical circuit to be simulated;
- and
- means for determining whether an active cell has become inactive and whether an inactive cell has become active;
- and
- means for shifting entries for active cells that have become inactive to the second sub-array and for shifting entries for inactive cells that have become active to the first sub-array.
Dependencies are inferred from the claim text.