Hybrid trace back apparatus and high-speed viterbi decoding system using the same

A hybrid trace back apparatus having a fully parallel add compare select (ACS) structure using a Radix4, the hybrid trace back apparatus comprising:

• a register exchanging means for receiving survivor values of each states, from a path metric calculator, and obtaining a block survival value through a register exchange operation as much as a bit length for a block trace back operation;
• a storing means for storing and outputting a block survival value to perform the register exchange operation, and storing the block survival value obtained through the register exchange operation until the block survival value is written in a block trace back memory;
• and
• a block trace back means for outputting decoded data by performing a block trace back operation while writing a value of the second storing means.

A high-speed Viterbi decoding system for performing a trace back operation, comprising:

• a register exchanging means for receiving survivor values of each state, from a path metric calculator, and obtaining a block survival value through a register exchange operation as much as a bit length for a block trace back operation;
• a first storing means for the register exchange operation;
• a second storing means for storing the block survival value obtained through the register exchange operation until the block survival value is written in a block trace back memory;
• and
• a block trace back means for outputting decoded data by performing a block trace back operation while writing a value of the second storing means,
• wherein the high-speed Viterbi decoding system decodes a convolutional code having a constraint length of 7 or 9 through a hybrid trace back operation combined with a register exchange and a block trace back under a structure having a fully parallel add compare select (ACS) path metric using a Radix4.