Memory system and semiconductor memory device
AssigneeFujitsu Limited
InventorsKuninori Kawabata, Satoshi Eto, Yasuhiro Onishi, Akira Kikutake
Life of this patent
Estimating the term…
Abstract
A memory system that can enhance yield without increasing the chip size and without degrading the access time. A single-bit error determination circuit references parity bits required to configure a code capable of correcting a single-bit error, and determines a single-bit error to be corrected; and a double-bit error detection circuit references one redundant bit added to the parity bits, detects a double-bit error, and enables or disables the double-bit error detection in accordance with a selection signal.
Claims10
A memory system having a function to detect and correct an error bit, the memory system comprising:
- a determination circuit for referencing data bits stored in a memory core and parity bits required to configure a code capable of correcting a single-bit error, and for determining a single-bit error to be corrected;
- and
- a detection circuit having a function to detect a double-bit error by referencing the data bits and one redundant bit added to the parity bits, for enabling and disabling the double-bit error detection in accordance with a selection signal.
A semiconductor memory device having a function to detect and correct an error bit, the semiconductor memory device comprising:
- a determination circuit for referencing data bits stored in a memory core and parity bits required to configure a code capable of correcting a single-bit error, and for determining a single-bit error to be corrected;
- and
- a detection circuit having a function to detect a double-bit error by referencing the data bits and one redundant bit added to the parity bits, for enabling and disabling the double-bit error detection in accordance with a selection signal.
Dependencies are inferred from the claim text.