LSI device having scan separators provided in number reduced from signal lines of combinatorial circuits

A semiconductor integrated circuit comprising a first circuit block, a second circuit block and a plurality of scan separators transferring, in ordinary operation, signals between said first and second circuit blocks and isolating, in testing operation, said first and second circuit blocks from each other, wherein

• each of said plurality of scan separators is provided for four of the signals transferred from said first circuit block to said second circuit block, and interconnected in cascaded stages,
• each of said plurality of scan separators comprising:
• a first selector for selecting one of the four signals output from said first circuit block in accordance with a combination of a first input selector signal and a second input selector signal, the first input signal being scan data supplied from outside or from one of the plurality of scan separators in one of the cascaded stages which precedes;
• a second selector for selecting scan data supplied from outside or from one of the plurality of scan separators in one of the cascaded stages which precedes when receiving a scan control signal, said second selector being adapted for selecting an output signal of said first selector when not receiving the scan control signal;
• a flip flop for holding an output signal of said second selector to output the output signal in a form of scan data to outside or to one of said plurality of scan separators which follows in the cascaded stages, and for sending the output signal to said first selector as the second input selector signal in response to a clock signal;
• and
• a third selector for selecting the four signals or the output signal of said flip flop in response to an output selector signal, and for affording a selected signal to said second circuit block.

A semiconductor integrated circuit comprising a first circuit block, a second circuit block and a plurality of scan separators transferring, in ordinary operation, signals between said first and second circuit blocks and isolating, in testing operation, said first and second circuit blocks from each other, wherein

• each of said plurality of scan separators is provided for two of the signals transferred from said first circuit block to said second circuit block, and interconnected in cascaded stages,
• each of said scan separator comprising:
• a first selector for selecting the two signals output from said first circuit block or a holding signal in response to an output selector signal to afford a selected signal to said second circuit block;
• a second selector for selecting one of the two signals output from said first selector in response to an input selector signal;
• a third selector for selecting scan data supplied from outside or from one of the plurality of scan separators in one of the cascaded stages which precedes when receiving a scan control signal, said third selector being adapted for selecting an output signal of said second selector when not receiving the scan control signal;
• and
• a flip flop for holding an output signal of said third selector to output the output signal in a form of scan data to outside or to one of said plurality of scan separators which follows in the cascaded stages, and for sending the output signal to said second selector as the input selector signal in response to a clock signal.

A semiconductor integrated circuit comprising a first circuit block, a second circuit block and a plurality of scan separators transferring, in ordinary operation, signals between said first and second circuit blocks and isolating, in testing operation, said first and second circuit blocks from each other, wherein

• each of said plurality of scan separators is provided for an even number of the signals transferred from said first circuit block to said second circuit block, and interconnected in cascaded stages,
• each of said plurality of scan separators comprising:
• a first selector for selecting one of the even number of the signals output from said first circuit block in accordance with a combination of a first input selector signal and a second input selector signal, the first input signal being scan data supplied from outside or from one of the plurality of scan separators in one of the cascaded stages which precedes;
• a second selector for selecting scan data supplied from outside or from one of the plurality of scan separators in one of the cascaded stages which precedes when receiving a scan control signal, said second selector being adapted for selecting an output signal of said first selector when not receiving the scan control signal;
• a flip flop for holding an output signal of said second selector to output the output signal in a form of scan data to outside or to one of said plurality of scan separators which follows in the cascaded stages, and for sending the output signal to said first selector as the second input selector signal in response to a clock signal;
• and
• a third selector for selecting the four signals or the output signal of said flip flop in response to an output selector signal, and for affording a selected signal to said second circuit block.