Random access memory having test circuit
AssigneeInfineon Technologies AG
InventorWolfgang Hokenmaier
Life of this patent
Estimating the term…
Abstract
A memory circuit comprises a memory and a first test circuit coupled to the memory. The first test circuit is configured to compare data read from memory cells with expected data for the memory cells to provide a first set of pass/fail signals for the memory cells, compress the first set of pass/fail signals for the memory cells into a second pass/fail signal, latch the second pass/fail signal in response to a data valid signal, maintain the latch of the second pass/fail signal if the second pass/fail signal indicates a failed test, combine the second pass/fail signal and a third pass/fail signal of a second test circuit to provide a fourth pass/fail signal, and pass the fourth pass/fail signal to a third test circuit.
Claims25
A memory circuit comprising:
- a memory;
- and
- a first test circuit coupled to the memory, the first test circuit configured to:
- compare data read from memory cells with expected data for the memory cells to provide a first set of pass/fail signals for the memory cells;
- compress the first set of pass/fail signals for the memory cells into a second pass/fail signal;
- latch the second pass/fail signal in response to a data valid signal;
- maintain the latch of the second pass/fail signal if the second pass/fail signal indicates a failed test;
- combine the second pass/fail signal and a third pass/fail signal of a second test circuit to provide a fourth pass/fail signal;
- and
- pass the fourth pass/fail signal to a third test circuit.
A memory comprising:
- a first array of memory cells;
- a plurality of compare circuits configured to compare data read from a portion of the first array of memory cells with expected data for the portion of the first array of memory cells to provide a first set of pass/fail signals for the portion of the first array of memory cells;
- a first compression circuit configured to compress the first set of pass/fail signals into a second pass/fail signal;
- a latch configured to latch the second pass/fail signal in response to a data valid signal;
- and
- a merge circuit configured to merge the second pass/fail signal with a third pass/fail signal to provide a fourth pass/fail signal indicating the pass/fail status for the first array of memory cells.
A memory comprising:
- means for writing expected data to a portion of an array of memory cells;
- means for reading data from the portion of the array of memory cells;
- means for comparing the data read from the portion of the array of memory cells to the expected data to provide a set of first pass/fail signals for the portion of the array of memory cells, each memory cell in the portion of the array of memory cells having one first pass/fail signal;
- means for merging the set of first pass/fail signals for the portion of the array of memory cells to provide a second pass/fail signal;
- and
- means for latching the second pass/fail signal in response to a data valid signal.
A method for testing a memory, the method comprising:
- comparing data read from a first set of memory cells of a first memory bank with expected data for the first set of memory cells to provide a first set of pass/fail signals for the first set of memory cells;
- compressing the first set of pass/fail signals for the first set of memory cells into a second pass/fail signal;
- latching the second pass/fail signal in response to a data valid signal;
- and
- maintaining the latch of the second pass/fail signal in response to subsequent data valid signals if the second pass/fail signal indicates a failed test.
A method for testing a memory, the method comprising:
- simultaneously writing expected data to memory cells of a plurality of memory banks of a memory;
- simultaneously reading data from the memory cells of the plurality of memory banks of the memory;
- simultaneously comparing the data read from the memory cells to the expected data to provide a test result for each memory bank;
- and
- combining the test result for each memory bank into a global test result for the memory.
Dependencies are inferred from the claim text.