# US 2006/0136768 A1 · Method and system for multi-program clock recovery and timestamp correction

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2006/0136768 A1
- Document ID: US20060136768A1
- Status: Published application
- Kind: A1
- Application number: 10/996,582
- Filed: 2004-11-23
- Published: 2006-06-22
- Earliest claimed: 2004-11-23
- Assignees: BroadLogic Network Technologies, Inc.
- Inventors: Binfan Liu; Thomas Ayers; Weimin Zhang
- Web page: https://patentgrep.com/patent/US20060136768A1

## CPC

- H04N 21/4305: {Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets (arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083)}
- H04N 21/426: Internal components of the client {; Characteristics thereof} (H04N5/44 takes precedence)
- H04N 21/43072: {of multiple content streams on the same device}
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.

## Claims

### Claim 1

A decoding system for decoding a set of programs comprising:
a transport engine configured to receive a set of programs and extract from each program a set of timing information and a set of timestamps embedded in the program;
an adder configured to add a timing offset from a set of timing offsets to each of the sets of timing information to adjust the sets of timing information from a first time basis to a second time basis, wherein sums of the timing offsets and the timing information are referred to the mapped-timing information, and the programs are associated, respectively, with the timing offsets;
a correction engine configured to update the timing offsets as timing information is encountered in the programs;
an offset register configured to:
receive the timing offsets from the correction engine,
store the timing offsets, and
transfer these timing offsets to the adder,
wherein the adder is configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis, and wherein sums of the timing offsets and the timestamps are referred to as a mapped timestamps; and
a program decoder configured to receive the mapped timestamps to decode the programs.

### Claim 2 (depends on 1)

The decoding system of claim 1, wherein:
each of the timing offsets is associated with one of the sets of timing information and one of the sets of timestamps, and
the adder is configured to add associated timing offsets and timing information, and add associated timing offsets and timestamps.

### Claim 3 (depends on 1)

The decoding system of claim 1, wherein the first time basis is an encoder-clock time basis, and the second time basis is a decoder-clock time basis.

### Claim 4 (depends on 1)

The decoding system of claim 1, wherein the set of programs are configured to be transported in a transport stream.

### Claim 5 (depends on 1)

The decoding system of claim 1, wherein:
the adder includes a first adder and a second adder,
the first adder is configured to add the timing offsets to the timing information, and
the second adder is configured to add the timing offsets to the timestamps.

### Claim 6 (depends on 1)

The decoding system of claim 1, wherein the timing information includes encoder-clock timing information.

### Claim 7 (depends on 1)

The decoding system of claim 1, wherein the timing information includes time information and frequency information.

### Claim 8 (depends on 1)

The decoding system of claim 1, wherein the set of programs includes two or more programs and the program decoder is configured to substantially simultaneously decode the set of programs.

### Claim 9 (depends on 1)

The decoding system of claim 1, wherein the timing offset includes timing information for timing differences between the first time basis and the second time basis.

### Claim 10 (depends on 1)

The decoding system of claim 1, wherein:
the timing information includes program-clock references (PCRs),
the timestamps include one or both of a set of presentation timestamps (PTSs) and a set of decoding timestamps, (DTS), and
the timing offsets include PCR offsets.

### Claim 11 (depends on 1)

The decoding system of claim 1, wherein the correction engine includes:
a decoder clock configured to generate a decoder-clock signal;
a local-time counter configured to receive the decoder-clock signal and accumulate the decoder-clock signal to generate accumulated-clock signals
a comparator configured to calculate differences between the accumulated-clock signals and the mapped-timing information, wherein the differences are the set of timing offsets;
a digital low pass filter (LPF) configured to receive the set of timing offsets from the comparator and filter the set of timing offsets; and
a digital phase lock loop (PLL) configured to receive the set of timing offsets from the digital LPF and reduce jitter in the set of timing offsets, wherein the digital PLL is configured to transfer the set of timing offsets to the offset register.

### Claim 12 (depends on 1)

The decoding system of claim 1, further comprising an offset selector configured to filter the timing offsets retrieved from the offset register.

### Claim 13 (depends on 12)

The decoding system of claim 12, wherein the transport engine includes:
a packet-identification (PID) table configured to store a program number and a set of PID numbers for each program; and
a packet-identification (PID) filter configured to:
extract PID numbers embedded in the programs,
transfer the PID numbers to the PID table to retrieve the program numbers associated with the PID numbers, and
transfer the program numbers to the offset selector to select the timing offsets associated with the program numbers.

### Claim 14

A decoding system for decoding a set of programs comprising:
a transport engine configured to receive a plurality of programs transported in a transport stream, and extract program-clock references (PCRs) and timestamps from the programs;
an adder configured to add the PCRs with PCR offsets to adjust the PCRs from an encoder-clock basis to a decoder-clock basis, wherein the sums are referred to as the mapped PCRs, each of the programs is associated with a PCR offset, and the PCR offsets represent timing differences between the encoder-clock basis and the decoder-clock basis;
a correction engine configured to update the PCR offsets as PCRs are encountered in the programs;
an offset register configured to receive the PCR offsets from the correction engine and transfer the PCR offsets to the adder, wherein the adder is configured to add the PCR offsets to the timestamps to map the timestamps from the encoder-clock basis to the decoder-clock basis, wherein summed timing offsets and timestamps are referred to as a mapped timestamps; and
a program decoder configured to receive the mapped timestamps to decode the program substantially simultaneously.

### Claim 15 (depends on 14)

The decoding system of claim 14, wherein the timestamps include presentation timestamps (PTSs) and/or decoding timestamps (DTSs).

### Claim 16 (depends on 14)

The decoding system of claim 14, wherein the correction engine includes:
a decoder clock configured to generate a decoder-clock signal in the decoder-clock basis;
a local-time counter configured to accumulate the decoder-clock signal to generate accumulated-clock signals;
a comparator configured to calculate differences between the accumulated-clock signals and the mapped PCRs, wherein the differences are the PCR offsets;
a digital low pass filter (LPF) configured to receive the PCR offsets from the comparator and filter the PCR offsets; and
a digital phase lock loop (PLL) configured to receive the PCR offsets from the digital LPF and reduce jitter in the PCR offsets, wherein the digital PLL is configured to transfer the PCR offsets to the offset register.

### Claim 17

A multi-program decoding method comprising:
receiving a transport stream that includes a plurality of programs;
extracting, from each program, a set of program-clock references (PCRs) and a set of timestamps that are associated with a first timing basis;
generating, based on the PCRs and a decoder-clock signal, a set of timing offsets that represents a difference between the first timing basis and a second timing basis, wherein each timing offset is associated with one of the programs and with this programs PCRs and timestamps;
adding the timing offsets, respectively, to the timestamps respectively associated with the timing offsets to adjust the timing basis of the timestamps from the first timing basis to the second timing basis; and
decoding one or more of the plurality of programs based on the timestamps adjusted to the second timing basis.

### Claim 18 (depends on 17)

The method of claim 17, wherein the step of generating the set of timing offsets includes:
mapping the PCRs from the first timing basis to the second timing basis based on the timing offsets, wherein the PCRs in the second timing basis are referred to as the mapped PCRs; and
generating differences between the mapped PCRs and the decoder-clock signals, wherein the differences are the timing offsets.

### Claim 19 (depends on 18)

The method of claim 18, wherein the decoder-clock signals are accumulated-decoder-clock signals.

### Claim 20 (depends on 18)

The method of claim 18, wherein the step of generating the set of timing offsets further includes:
digitally filtering the differences; and
digitally locking onto the differences for jitter correction.

### Claim 21 (depends on 18)

The method of claim 18, wherein the step of mapping the PCRs from the first timing basis to the second timing basis includes, adding the PCRs to the PCRs' respectively associated timing offsets.

### Claim 22 (depends on 18)

The method of claim 18, wherein the step of generating the timing offsets includes, for each timing offset, updating the timing offset for each of the PCRs received in the program associated with the timing offset as the PCRs are encountered in the program by repeating the steps of mapping the PCRs, and generating the differences.

### Claim 23 (depends on 17)

The method of claim 17, and further comprising:
storing the timing offsets in a register; and
retrieving the timing offsets from a register to add the timestamps and timing offsets that are associated with the timestamps.

### Claim 24 (depends on 17)

The method of claim 17, and further comprising:
extracting a program identifier (PID) from each of the programs as the PIDs are encountered in the programs; and
transferring each of the PIDs to a PID table;
based on the transferring step, retrieving from the PID table a program number for each of the programs; and
transferring the programs numbers to a selector circuit to retrieve the timing offsets respectively associated with the programs.

### Claim 25 (depends on 17)

The method of claim 17, wherein the first timing basis is an encoder-clock basis and the second timing basis is a decoder-clock basis.

### Claim 26 (depends on 17)

The method of claim 17, wherein the timing offsets are (PCR) offsets.