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US 2006/0136755 A1Published application
System, apparatus, and method to enable and disable a mode of operation of a stacked circuit arrangement on an independent circuit basis using register bits and a single shared mode control line
OwnerShekoufeh Qawami, Mark Leinwander +1inventors
InventorsShekoufeh Qawami, Mark Leinwander, Chaitanya Rajguru
Life of this patent
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Abstract
System, apparatus, and method to enable and disable a mode of operation of a stacked circuit arrangement on an independent circuit basis using register bits and a single shared mode control line.
Claims46
An apparatus, comprising:
- a first circuit, wherein said first circuit comprises:
- a first register;
- a first input to receive a first control signal to control a polarity of a status bit of said first register;
- and
- a second input to receive a second control signal;
- wherein a mode of operation of said first circuit is enabled by controlling said polarity of said status bit of said first circuit and a polarity of said second control signal.
3 more elements
A system, comprising:
- an antenna;
- a network interface connected to said antenna;
- and
- a device connected to said interface, said device to include:
- a first register;
- a first input to receive a first control signal to control a polarity of a status bit of said first register;
- a second input to receive a second control signal;
- and
- wherein a mode of operation of said first circuit is enabled by controlling said polarity of said status bit of said first circuit and a polarity of said second control signal.
6 more elements
The system of 17, further comprising:
- a second circuit, wherein said second circuit comprises:
- a first register;
- a first input to receive a first control signal to control a polarity of a status bit of said first register;
- and
- a second input to receive said second control signal;
- wherein a mode of operation of said second circuit is enabled by controlling said polarity of said status bit of said second circuit and a polarity of said second control signal.
3 more elements
A system, comprising:
- a processor;
- a memory connected to said processor, said memory to include:
- a first register;
- a first input to receive a first control signal to control a polarity of a status bit of said first register;
- and
- a second input to receive a second control signal;
- wherein a mode of operation of said first circuit is enabled by controlling said polarity of said status bit of said first circuit and a polarity of said second control signal.
4 more elements
The system of 30, further comprising:
- a second circuit, wherein said second circuit comprises:
- a first register;
- a first input to receive a first control signal to control a polarity of a status bit of said first register;
- and
- a second input to receive said second control signal;
- wherein a mode of operation of said second circuit is enabled by controlling said polarity of said status bit of said second circuit and a polarity of said second control signal.
3 more elements
A method, comprising:
- enabling a mode in a selected number of a plurality of devices;
- setting a polarity of a common mode signal;
- providing said common mode signal to a plurality of devices;
- and
- individually placing said selected devices in said mode.
2 more elements
Dependencies are inferred from the claim text.