Vector processing system
AssigneeBroadcom Corporation
InventorsStephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
Life of this patent
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Abstract
A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.
Claims21
1-20. (canceled)
An integrated circuit comprising:
- a circuit for receiving an instruction that defines:
- multiple value pairs,
- an operation to be executed, and
- a scalar modifier;
- a plurality of co-processors, wherein each co-processor is arranged to receive one of said value pairs and implement the defined operation on said value pair to generate a respective result, and wherein each of the plurality of co-processors is identified by an index;
- and
- a post-processor for receiving the results of the plurality of co-processors and for using said results in a manner defined by the scalar modifier to return the index of one of the co-processors.
An integrated circuit comprising:
- a first circuit for performing an operation on a plurality of value pairs to generate a plurality of intermediate outputs, wherein each intermediate output is identified by an index;
- and
- a second circuit for receiving the plurality of intermediate outputs and returning the index of one intermediate output according to a predefined condition.
Dependencies are inferred from the claim text.