Method and apparatus for address translation

A method for translating a memory address comprising:

• requesting data at a virtual address;
• checking a memory management unit cache for presence of an address translation entry hit indicating that the virtual address is in the memory management unit cache and providing an address translation entry from the memory management unit cache;
• translating the virtual address to a physical address using the address translation entry if there is a hit and performing a data access at the physical address;
• when no hit occurs, hashing the virtual address to obtain one or more possible physical addresses of the address translation entry;
• performing a prefetch of the one or more physical addresses from a main memory into a data cache;
• determining if the address translation entry is still required;
• if the address translation entry is still required, peforming a tablewalk to search for a matching address translation entry from the one or more physical addresses prefetched from the main memory into the data cache;
• loading the matching address translation entry into the memory management unit cache;
• translating the virtual address to a corresponding physical address using the matching address translation entry;
• and
• performing a data access at the corresponding physical address.

A method for translating memory addresses, comprising:

• providing data processing instructions from an instruction cache;
• buffering and executing the data processing instructions with at least a memory access sub-pipeline;
• executing memory access instructions in the memory access sub-pipeline, the memory access instructions being contained within the data processing instructions;
• selectively providing a translated memory address entry in response to receiving a virtual address;
• when the translated memory address entry is not stored within a memory management unit cache, providing one or more addresses defining possible locations of a desired address translation entry;
• holding prefetch requests in a prefetch queue, the prefetch queue receiving the possible locations of the desired address translation entry and providing a prefetch request of the desired address translation entry in response to detecting a speculative address translation miss and prior to flushing the memory access sub-pipeline;
• selectively storing data corresponding to physical memory addresses in a data cache and storing all data corresponding to physical memory addresses in a main memory;
• and
• determining whether data corresponding to the possible locations of the desired address translation entry is resident in the data cache, and if not, obtaining data corresponding to the possible locations of the desired address translation entry from the main memory, and loading the data to the data cache;
• wherein the data is searched for a match with the desired address translation entry, and upon detection of the match the desired address translation entry is loaded into the memory management unit cache.