Detection circuit for mixed asynchronous and synchronous memory operation

A mode detection circuit for initiating a memory access operation in a memory device receiving memory address signals and control signals, the detection circuit comprising:

• a first mode detection circuit operable to generate a first mode detection signal to be provided at a first output node in response to receipt of the memory address signals and receipt of control signals requesting an asynchronous memory access operation;
• a second mode detection circuit operable to generate a second mode detection signal to be provided at a second output node in response to receipt of an active clock signal and receipt of control signals requesting a synchronous memory access operation;
• a delay circuit coupled to the first and second mode detection circuits, the delay circuit operable to provide a delayed mode detection signal in response to a last received first mode detection signal and further operable to interrupt provision of the delayed mode detection signal in response to the second mode detection signal;
• and
• an output circuit coupled to the second mode detection circuit and the delay circuit, the output circuit operable to provide an activation signal to initiate a memory access operation in response to the delayed mode detection signal or the second mode detection signal.

A memory device, comprising:

• an array of memory cells;
• memory array access circuit coupled to the array of memory cells for accessing the memory array;
• and
• a memory access mode detection circuit coupled to receive command signals, the memory access mode detection circuit comprising:
• an asynchronous operation command detection circuit operable to generate a delayed memory operation activation pulse in response to receipt of command signals corresponding to a request for an asynchronous memory operation, the delayed memory operation activation pulse delayed by a minimum delay time relative to receipt of the command signals;
• and
• a synchronous operation command detection circuit operable to generate a memory operation activation pulse in response to receipt of command signals corresponding to a request for a synchronous memory operation and further operable to suppress generation of a delayed memory operation activation pulse by the asynchronous operation command detection circuit, the memory operation activation pulse generated by the synchronous operation command detection circuit in less time relative to receipt of the command signals than the minimum time delay.

A method for initiating a memory operation in response to receiving command signals, comprising:

• in response to the command signals requesting an asynchronous memory operation, generating a memory operation activation pulse a time delay following receipt of the most recently received command signals requesting an asynchronous memory operation;
• in response to the command signals requesting a synchronous memory operation, generating the memory operation activation pulse sooner after receipt of the command signals than the time delay associated with an asynchronous memory operation;
• and
• initiating a memory operation in response to the memory operation activation pulse.