Method and apparatus for arbitrarily initializing a portion of memory

An apparatus for routing information in a data packet, comprising:

• a network interface that is coupled to a network for communicating therewith a data packet;
• a memory for storing information;
• one or more processors;
• a data communication channel connected to the one or more processors;
• a memory controller circuit block connected to the memory and connected to the data communication channel and configured to perform the steps of:
• receiving on the data communication channel address data that indicates a location in memory,
• length data that indicates an amount of memory to be initialized, and
• pattern data that indicates a particular series of bits that is much shorter than the amount of memory indicated by the length data;
• and
• performing a plurality of write operations to memory beginning at a first location in memory based on the address data and ending at a second location in memory based on the length data, wherein each write operation of the plurality of write operations writes the pattern data to a current location in memory, whereby an arbitrary portion of memory is initialized with an arbitrary pattern based on the pattern data;
• and
• one or more sequences of instructions in a computer-readable medium, which, when executed by the one or more processors, causes the one or more processors to perform the steps of:
• initializing the arbitrary portion of memory for at least one of storing, routing and sending the data packet by sending to the memory controller the address data, the length data and the pattern data, thereby omitting processor clock cycles that would otherwise be consumed in repeatedly sending the pattern data on the data communication channel for a plurality of memory locations in a range from the first location to the second location;
• and
• performing at least one of storing, routing and sending the data packet based at least in part on information subsequently stored in the arbitrary portion of memory.

A memory controller for performing sequenced read and write operations to a computer memory, comprising:

• a means for receiving on a data communication channel connected to a processor address data that indicates a location in memory,
• length data that indicates an amount of memory to be initialized, and
• pattern data that indicates a particular series of bits that is much shorter than the amount of memory indicated by the length data;
• and
• a means for performing a plurality of write operations to memory beginning at a first location in memory based on the address data and ending at a second location in memory based on the length data, wherein each write operation of the plurality of write operations writes the pattern data to a current location in memory, whereby an arbitrary portion of memory is initialized with an arbitrary pattern based on the pattern data.

An apparatus for routing information in a data packet, comprising:

• a memory for storing information;
• one or more processors;
• a data communication channel connected to the one or more processors;
• a means for communicating a data packet;
• a means for sending on the data communication channel, from the one or more processors
• address data that indicates a location in memory,
• length data that indicates an amount of memory to be initialized, and
• pattern data that indicates a particular series of bits that is much shorter than the amount of memory indicated by the length data;
• a means for receiving the address data, length data and pattern data on the data communication channel;
• and
• a means for performing a plurality of write operations to memory beginning at a first location in memory based on the address data and ending at a second location in memory based on the length data, wherein each write operation of the plurality of write operations writes the pattern data to a current location in memory, whereby an arbitrary portion of memory is initialized with an arbitrary pattern based on the pattern data,
• whereby processor clock cycles are omitted that would otherwise be consumed in repeatedly sending the pattern data on the data communication channel for a plurality of memory locations in a range from the first location to the second location;
• and
• a means for performing at least one of storing, routing and sending the data packet based at least in part on information subsequently stored in the arbitrary portion of memory.

A method for a network device, which includes a general purpose processor configured to execute a router operating system, for initializing an arbitrary portion of memory with an arbitrary pattern, the method comprising the steps of:

• receiving a data packet at a network device;
• determining an arbitrary portion of memory to be initialized for performing at least one of storing, routing, and sending the data packet;
• determining a pattern of bits to use in initializing the portion of memory;
• sending, on a data communication channel connected to a memory controller,
• address data that indicates a location in memory based on the arbitrary portion of memory,
• length data that indicates a size of the portion of memory, and
• pattern data, based on the pattern of bits, which pattern data indicates a particular series of bits that is much shorter than the amount of memory indicated by the length data,
• whereby the memory controller performs a plurality of write operations to memory beginning at a first location in memory based on the address data and ending at a second location in memory based on the length data, wherein each write operation of the plurality of write operations writes the pattern data to a current location in memory,
• thereby omitting processor clock cycles that would otherwise be consumed in repeatedly sending, on the data communication channel, the pattern data for a plurality of memory locations in the arbitrary portion of memory;
• and
• performing at least one of storing, routing and sending the data packet based at least in part on information subsequently stored in the arbitrary portion of memory.

A computer-readable medium carrying one or more sequences of instructions for processing information in a payload of a first network protocol which payload includes header information for a second network protocol, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform the steps of:

• receiving a data packet at a network device;
• determining an arbitrary portion of memory to be initialized for performing at least one of storing, routing, and sending the data packet;
• determining a pattern of bits to use in initializing the portion of memory;
• sending, on a data communication channel connected to a memory controller,
• address data that indicates a location in memory based on the arbitrary portion of memory,
• length data that indicates a size of the portion of memory, and
• pattern data, based on the pattern of bits, which pattern data indicates a particular series of bits that is much shorter than the amount of memory indicated by the length data,
• whereby the memory controller performs a plurality of write operations to memory beginning at a first location in memory based on the address data and ending at a second location in memory based on the length data, wherein each write operation of the plurality of write operations writes the pattern data to a current location in memory,
• thereby omitting processor clock cycles that would otherwise be consumed in repeatedly sending the pattern data on the data communication channel for a plurality of memory locations in the portion of memory;
• and
• performing at least one of storing, routing and sending the data packet based at least in part on information subsequently stored in the arbitrary portion of memory.

A method for performing sequenced read and write operations on a computer memory, comprising the steps of:

• receiving on a first data communication channel connected to a processor address data that indicates a location in memory,
• length data that indicates an amount of memory to be initialized, and
• pattern data that indicates a particular series of bits that is much shorter than the amount of memory indicated by the length data;
• and
• sending a plurality of write operations on a second different data communication channel connected to a memory, beginning at a first location in memory based on the address data and ending at a second location in memory based on the length data, wherein each write operation of the plurality of write operations writes the pattern data to a current location in memory, whereby an arbitrary portion of memory is initialized with an arbitrary pattern based on the pattern data.